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IMPORTANT NOTE: THIS SITE IS NO MORE MAINTENED

Go here for the list of publications of 2012 and later

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Book chapters (Chapitres de livre)

  1. "Codes et Turbocodes", Collection IRIS, C. Berrou (Réd.), Springer, Paris, 2007, 397 p. (Iris), ISBN 978-2-287-32739-1
  2. E. Boutillon, C. Roland, M. Sevaux " Probability-driven simulated annealing for optimizing digital FIR filters", Studies in Computational Intelligence, Springer Berlin / Heidelberg, Vol. 136/2008, Pages 77-93, ISBN 978-3-540-79437-0.
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Journal papers (Publications dans des revues)

  1. H. Liu, C. Jeho, E. Boutillon, M. Jezequel, J.-P. Diguet “ A contribution to the reduction of the dynamic power dissipation in the turbo decoder", Annals of Telecommunications, vol 67, pp 397–406, july 2012.
  2. E. Boutillon, L. Conde-Canencia,“Bubble check: a simplified algorithm for elementary check node processing in extended min-sum non-binary LDPC decoders Electronics Letters / IEE Electronics Letters 46, 9 (2010) pp. 633-634 (2010).
  3. C. Marchand, L. Conde-Canencia, E. Boutillon, " Architecture and finite precision optimization for layered LDPC Decoders ", Journal of Signal Processing Systems, Springer, pp. 185-197, vol. 65, n°2, Nov. 2011.
  4. A. Al-Ghouwayel, E. Boutillon“ A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders", IEEE Communications Letters, vol. 15 , n°8, pp. 851 – 853, aug. 2011.
  5. H. Liu, C. Jégo, E. Boutillon, J-Ph. Diguet, and M. Jézéquel, “ Scarce state transition turbo decoding based on re-encoding combined with a dummy insertion", Electronics Letters, vol. 45, n°16, pp. 846-848, july 2009.
  6. A. Singh, A. Al-Ghouwayel1, G. Masera, E. Boutillon, " A New Performance Evaluation Metric for Sub-Optimal Iterative Decoders", IEEE Communications letters, vol. 13, n°7, pp. 513-515, July 2009.
  7. M. Ciesielski, D. Gomez-Prado, Q. Ren, J. Guillot, E. Boutillon, " Optimization of Data Flow Computations using Canonical TED Representation", IEEE Design & Test of Computers, vol. 26, n°4, pp:46 - 57, July-Aug. 2009.
  8. M. Ciesielski, J. Guillot, D. Gomez-Prado, Q. Ren, E. Boutillon, " High-level Transformations using Canonical Dataflow Representation", IEEE Transactions on Computer-Aided Design of Integrated Circuits, TCAD, vol. 28, n°9, pp. 1321-1333, Sept. 2009.
  9. A. Nafkha, E. Boutillon, C. Roland, " Quasi-Maximum-Likelihood Detector Based on Geometrical Diversification Greedy Intensification", IEEE Transactions On Communications, vol. 57, n°4, pp. 926-929, April 2009.
  10. F. Guilloud, E. Boutillon, J. Tousch, J.L. Danger, "Generic description and synthesis of LDPC decoder", IEEE Transactions On Communications, IEEE Transactions on Communications, Vol. 55, n°11, pp 2084 - 2091, nov. 2007..
  11. E. Boutillon, C. Douillard, G. Montorsi, " Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues", Transactions of the IEEE, vol. 95, n°6, june 2007.
  12. C. Cunat, E. Boutillon, " Simplified hardware bit correlator", IEEE Communication Letters, vol. 11, n°6, june 2007.
  13. E. Boutillon, D. Gnaëdig, "Maximum Spread of D-dimensional Multiple Turbo Codes", IEEE Transactions on Communications, vol. 53, no. 8, aug. 2005
  14. D. Gnaëdig, E. Boutillon, M. Jezequel, V. Gaudet, G. Gulak, "On Multiple Slice Turbo Code", D. Gnaëdig, E. Boutillon, M. Jezequel, V. Gaudet, G. Gulak, Annals of Telecommunications, Vol. 60, n°1-2, janvier-février 2005..
  15. D. Gnaedig, E. Boutillon, M. Jézéquel, "Design of Three-Dimensional Multiple Slice Turbo Codes", Special Issue on Turbo Processing, EURASIP Journal on Applied Signal Processing, vol 2005 n°6, may 2005, pp 808-819..
  16. D. Gnaedig, E. Boutillon, E. Martin, A. Nafkha, J. Tousch, M. Jézéquel, N. Brengarth "Synthèse d’architecture pour la réalisation comportementale de l’algorithme MAP pour Turbo Décodeur", Les Annales des Télécommunications, vol. 59, n°3-4, Avril 2004, pp 321-344
  17. E. Boutillon, W.J. Gross, G. Gulak, "VLSI architectures for the MAP Algorithm", IEEE Transactions on Communications, Vol. 51, No. 2. February 2003. pp. 175-185.
  18. E. Boutillon, J.L. Danger, A. Gazel, " Design of High Speed AWGN Communication Channel Emulator", Kluwer Press, Analog Integrated Circuits and Signal Processing 34(2): 133-142; Feb 2003
  19. E. Boutillon, J.L. Danger, Y. Mathieu, "Evolution du métier de concepteur de systèmes électronique numériques", Les cahiers du numériques, Volume 1, n°3-2000, Hermès Science Publications, pages 113 à 124.
  20. X. Giraud, E. Boutillon and J.C. Belfiore, "Algebraic tools to build modulation schemes for fading channels", IEEE Trans. on Information Theory, vol. 43, May 1997.
  21. E. Boutillon, J.M. Urunuela, "Decoding of constellations matched to the Rayleigh fading channel", Les annales des telecommunications,vol.53, no.1-2; Jan.-Feb. 1998; p.28-38.
  22. E. Boutillon, J.M. Urunuela, "A VLSI decoder for a new type of constellations adapted to the rayleigh Fading Channel", Special issue on VLSI for wireless communication, Wireless Network, p.17-26, ACM, 1998.
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International Symposiums (Colloques internationaux)

  1. C. Marchand, M. Hammouda, Y. Eustache, L. Conde-Canencia, E. Boutillon, Design and implementation of a near maximum likelihood decoder for Cortex codes, 7th International Symposium on Turbo Codes & Iterative Information Processing, Gothenburg, Sweden, august 2012.
  2. C. Winstead, Y. Tang,, E. Boutillon, C. Jego, Christophe and M. Jézéquel, A Space-Time Redundancy Technique for Embedded Stochastic Error Correction, 7th International Symposium on Turbo Codes & Iterative Information Processing, Gothenburg, Sweden, august 2012.
  3. Y. Tang,C. Winstead, E. Boutillon, C. Jego, Christophe and M. Jézéquel, An LDPC decoding method for fault-tolerant digital logic<\A>, IEEE International Symposium on Circuits and Systems (ISCAS), pp: 3025-3028, Seoul, may 2012.
  4. E. Boutillon, P. Kim, C. Roland and D.-G. Oh, "Efficient Multiplierless Architecture for Frame Synchronization in DVB-S2 Standard", SISP 2011, Oct. 2011, Beirut
  5. Y. Tang, E. Boutillon, C. Jégo and M. Jézéquel, "Harware Efficiency Versus Error Probability In Unreliable Computation", SISP 2011, Oct. 2011, Beirut
  6. M. Awais, A. Singh, E. Boutillon, G. Masera, "A Novel Architecture for Scalable, High throughput, Multi-standard LDPC Decoder",14th Euromicro conference on Digital System Design Architectures, Methods and Tools, DSD 2011, Sept. 2011, Oulu, Finland
  7. Y. Tang, E. Boutillon, C. Jégo and M. Jézéquel, "A new single-error correction scheme correction scheme based on self-diagnosis residue number arithmetic", DASIP 2010, Oct. 2010, Edhinburg
  8. D. Gomez-Prado, K. Du-Sung, M. Ciesielski, E. Boutillon, "Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams", High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE Internationa, pp 33-39, June 2010
  9. C. Marchand, L. Conde-Canencia, E. Boutillon, "Architecture and finite precision optimization for layered LDPC decoders", Processing Systems (SIPS’2010), San Franscisco, Oct 2010.
  10. E. Boutillon, Y. Tang, C. Marchand, P. Bomel, “Hardware Discrete Channel Emulator”, The 2010 International Conference on High Performance Computing & Simulation (HPCS 2010), pp 452-458, Caen, June 2010.
  11. C. Marchand, J.-B. Doré, L. Conde-Canencia, E. Boutillon, "Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders", Globecom 2009, Haiwai, Dec. 2009.
  12. C. Marchand, J.-B. Doré, L. Conde-Canencia, E. Boutillon,"Conflict resolution for pipelined layered LDPC decoders", SIPS 2009, Tampere, Oct. 2009.
  13. A. Courtay, E. Boutillon, J. Laurent, "A convolutional code for on-chip interconnect Crosstalk Reduction", IEEE International Symposium on Circuits and Systems, ISCAS 2009. pp 145-148, Taipei, 2009.
  14. L. Conde-Canencia, A. Al-Ghouwayel, E. Boutillon," Complexity Comparison of Non-Binary LDPC Decoders", ICT-MobileSummit, Santander, 2009.
  15. C. Poulliat, D. Declercq, L.Conde-Canencia, A. Al-Ghouwayel and E. Boutillon, "Non-Binary LDPC Codes defined over General Linear Group: finite length design and practical implementation issues", IEEE 69th Vehicular Technology Conference (VTC'2009), Barcelona, April 2009.
  16. D. Gomez-Prado, M. Ciesielski, J. Guillot, E. Boutillon, "Optimizing Data Flow Graphs to Minimize Hardware Implementation" Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE'09, pp 117-122, Nice, April. 2009.
  17. A. Singh, E. Boutillon, G. Masera, "Bit-width Optimization of Extrinsic Informations in Turbo Decoder", 5th International Symposium on Turbo Codes & Related Topics, Lausanne, Sept. 2008.
  18. M. Scarpellino, A. Singh, E. Boutillon, G. Masera, "Reconfigurable Architecture for LDPC and Turbo Decoding: A NoC Case Study", ISSSTA 2008, Bologna, Aug. 2008.
  19. A. Dion, L.V. Calmettes, E. Boutillon, E. Liegeon, " Fast Acquisition Unit for GPS/GALILEO Receivers in Space Environment", ION GNSS 2008, San Diego, Jan., 2008.
  20. P. Chatellier, E. Boutillon, P. Tortelier, " Toward a real time SIMO channel emulator ", WIMOB 2007, 3rd IEEE int. conf. on Wireless and Mobile Computing, Networking and Communications, New York, USA, Oct. 2007
  21. A. Dion, E. Boutillon, L.V. Calmettes, "Reconfigurable GPS-Galileo Receiver for Satellite-based Applications", ION GNSS 2007, Fort Worth, Texas, Sept., 2007.
  22. H. Liu, J.P. Diguet, C. Jego, M. Jézéquel, E. Boutillon, " Energy Efficient Turbo Decoder By Reducing The State Metric Quantization ", SIPS'07, Sanghai, China, Oct. 2007
  23. I. M. Mahafeno, L. Conde-Canencia, E. Boutillon, "Coarse Self-Synchonization Technique For GNSS Receivers ", SIPS'07, Sanghai, China, Oct. 2007
  24. M. Ciesielski, S. Askar, D. Gomez-Prado, J. Guillot, E. Boutillon "Data-Flow Transformations Using Taylor Expansion Diagrams ", Design Automation and Test in Europe 2007, DATE'2007, Nice, April 2007
  25. D. Gnaedig, E. Boutillon, J. Tousch, M. Jezequel, "Towards an optimal parallel decoding of turbo codes", 4th International Symposium on Turbo Codes & Related Topics, Munich, april 2006.
  26. J. Guillot, E. Boutillon, Q. Ren, M. Ciesielski, D. Gomez-Prado, S. Askar, "Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams", DATE'2006, Munich, 2006.
  27. P. Bomel, N. Abdelli, E. Martin, E. Boutillon, A.M. Fouilliart, P. Kajfasz, "DVB-DSNG modem High-Level Synthesis in an optimized Latency Insensitive System context", SAMOS, Greece, July 18 - 20, 2005.
  28. A. Nafkha, C. Roland, E. Boutillon, "A Near-Optimal Multiuser Detector for MC-CDMA systems Using Geometrical Approach" ICASSP'05, Philadelphia, Vol. 3, pp 877-80 Mars 2005.
  29. P. Bomel, E. Martin, E. Boutillon, "Synchronization Processor Synthesis for Latency Insensitive Systems" DATE'05, Munich, Mars 2005.
  30. D. Gomez-Prado, Q. Ren, S. Askar, M.Ciesielskin, E. Boutillon "Variable ordering for taylor expansion diagrams ", High-Level Design Validation and Test Workshop, HLDVT'04, pp 55-59, nov. 2004
  31. D. Gnaedig, M. Lapeyre, F. Mouchoux, E. Boutillon "Efficient SIMD technique with parallel Max-Log-MAP Algorithm for Turbo Decoders", accepted to GSPx 2004 Embedded Applications Software & Hardware , Santa Clara, CA USA, Sept. 27-30, 2004.
  32. P. Coussy, D. Gnaëdig, A. Nafkha, A. Baganne, E. Boutillon, E. Martin, "A Methodoly for IP integration in DSP Soc: a case study of a MAP algorithm for turbo decoder", ICASSP'04, Montreal, Vol.5, pp. 45-49, May 2004.
  33. D. Gnaëdig, E. Boutillon, M. Jezequel, V. Gaudet, G. Gulak, "On Multiple Slice Turbo Code", 3nd International Symposium on Turbo Codes and Related Topics, Brest, France, pp. 343-346, Sept. 2003
  34. F. Guilloud, E. Boutillon, J.L. Danger, "lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes", 3nd International Symposium on Turbo Codes and Related Topics, Brest, France, pp 451-454, Sept. 2003
  35. D. Derrien, E. Boutillon," "Quality Measurement of a Colored Gaussian Noise Generator Hardware Implementation Based on Statistical Properties", IEEE International Symposium on Signal Processing and Information Technology, Maroc, Déc. 2002.
  36. Priyank Kalla, Maciej Ciesielski, E. Boutillon, Eric Martin, "High-level Design Verification using Taylor Expansion Diagrams: First Results", Accepted to the Seventh Annual IEEE International Workshop on High Level Design Validation and Test, HLDVT'02, Cannes, Oct. 2002.
  37. F. Guilloud, E. Boutillon, J.L. Danger, "Bit Error Rate Calculation for a Multiband non coherent On-Off keying demodulation", IEEE Int. Conf. on Communications, ICC'02, New York, USA, pp 202-206, vol 1., 2002
  38. A. Gazel, E. Boutillon, J.L. Danger, G. Gulak, H. Lamaari,"Design and performance analysis of a high speed AWGN Communication Channel Emulator", (PACRIM'01), Victoria, British Colombia, Canada, August 2001
  39. J.L Danger, A. Ghazel, E. Boutillon H. Laamari,"Efficient FPGA Implementation of Gaussian Noise Generator for Communication Channel Emulation", Accepted for the 7th IEEE International Conference on Electronicsm Circuits & Systemes (ICECS'2K), , Kaslik, Lebanon, Dec 2000
  40. E. Boutillon, Jeff Castura, Frank R. Kschischang, "Decoder-First Code Design", Proceedings of the 2nd International Symposium on Turbo Codes and Related Topics, pp 459-462, Brest, France, Sept. 2000
  41. E. Boutillon, L. Gonzalez, "Joint Source-Channel Coding using Convolutional Codes'Partial Tranfer Function and the Forward-Backward Algorithm", Proceedings of the 2nd International Symposium on Turbo Codes and Related Topics, pp. 415-418, Brest, France, Sept. 2000
  42. L. Gonzalez, E. Boutillon, "Simplified Path Metric Updating in the M Algorithm for VLSI Implementation", Accepted for the 20000 International Conference on Acoustics, Speech and Signal Processing (ICASSP2000), Istambul, Turkey, June 2000
  43. E. Boutillon, L. Gonzalez, "Trace-Back Techniques Adapted to the Surviving Memory Management in the M Algorithm", Accepted for the 2000 International Conference on Acoustics, Speech and Signal Processing (ICASSP'2000), Istambul Turkey, June 2000
  44. L. Gonzalez, E. Boutillon, "Study of a Suboptiml VLSI Architecture for Joint Source-Channel Trellis Coding", Accepted for the 20000 International Symposium on Circuits and Systems (ISCAS'00), Geneva, Switzerland, May 2000
  45. E. Boutillon, A. Dehamel, "Reed-Solomon architecture for a smart Reed-Solomon Decoder", MWSCAS'99, New Mexico, Aug. 99.
  46. L. Gonzalez Perez, E. Boutillon, "A VLSI Architecture for Joint Source Channel Coding ", MWSCAS'99, New Mexico, Aug. 99.
  47. E. Boutillon, J.L Danger, "Implementation of a demodulator in FPGA", SIPS'98, Boston, Oct. 98.
  48. E. Boutillon, N. Demassieux, "High speed low power architecture for memory management in a Viterbi decoder", ISCAS'96, IEEE, Atlanta 1996; pp. p.284-7
  49. E. Boutillon, J.C. Belfiore, N. Demassieux, "A VLSI architecture for Trellis Coded Modulation using Constellations designed for the Rayleigh Channel", Proc. SUPERCOM/ICC, New-Orleans, May 1994.
  50. C. Verdier, E. Boutillon, A. Lafage, A. Demeure, "Access and Alignment of Arrays for a Bi-Dimensional Parallel Memory", ASAP 1994, San Francisco (USA).
  51. C. Verdier, A. Lafage, E. Boutillon, A. Demeure, "A Bi-Dimensional Chinese Interconnection Network for SIMD Architectures", MPCS'94, Ischia, Italy, mai 1994.
  52. C. Verdier, A. Lafage, E. Boutillon, A. Demeure, "A New Multi-Dimensional Interconnection Network for SIMD Architectures", PARLE'94, Athènes, Grèce, jul. 1994.
  53. E. Boutillon, N. Demassieux, "A generalized precompiling scheme for surviving path memory management in Viterbi decoders", ISCAS'93, IEEE, vol. 3, pp. 1579-82, New-Orleans, May 1993.
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National symposiums (Colloques nationaux)

  1. S. Trégaro, E. Boutillon, C. Roland," Architecture temps réel d’analyse temps/fréquence large bande", GRETSI'2009, Dijon, sept. 2009
  2. J. Guillot, E. Boutillon, M. Ciesielski, D. Gomez,"Optimisation automatique d'un Data Flow Graph à l'aide d'un formalisme TED. Cas d'étude: La Transformée de Fourier Discrète", GRETSI'2007, Troye, sept. 2007
  3. I. Masinjara Mahafeno, L. Conde-Canencia, E. Boutillon, "Technique d'auto-synchronisation grossière pour un récepteur GNSS", GRETSI'2007, Troye, sept. 2007
  4. E. Boutillon, M. Ciesielski, J. Guillot, M. Sevaux, "Application du recuit simulé pour l'optimisation des Taylor Expansion Diagrams", MAJESTIC 2007, Lorient, nov. 2007.
  5. H. Liu, J.-P. Diguet, C. Jego, E. Boutillon, M. Jezequel, "Etat de l'art sur la maîtrise de la consommation dans les turbocodes", MAJESTIC 2007, Lorient, nov. 2007.
  6. F. Guilloud, E. Boutillon, J. Tousch, "Description et synthèse générique des décodeurs de codes LDPC", Journées Francophones sur l’Adéquation Algorithme Architecture, Dijon, Janv. 2005.
  7. P. Bomel, E. Martin, E. Boutillon, "Architecture de wrapper de synchronisation pour environnement de type GALS/LIS", Journées Francophones sur l’Adéquation Algorithme Architecture, Dijon, Janv. 2005.
  8. D. Gnaëdig, E. Boutillon, M. Jezequel, Vincent Gaudet, Glenn Gulak, "Turbo-Codes à roulettes", accepted to the GRETSI 2003, Paris, Sept. 2003.
  9. F. Guilloud, E. Boutillon, J.-L. Danger, "Décodage des codes LDPC par l'algorithme lambda-Min", Accepted to the GRETSI 2003, Paris, Sept. 2003.
  10. E. Boutillon, D. Derrien, "Implémentation hardware d’un générateur de bruit de Rayleigh coloré", Journées Francophones sur l’Adéquation Algorithme Architecture, Tunisie, Déc. 2002.
  11. F. Guilloud, E. Boutillon, J.L. Danger, "Etude d'un algorithme itératif de repliement spectral lors d'une conversion A/N parralèle", 5eme Journees Nationales du Reseau Doctoral de Microelectronique, Grenoble, Avril 2002.
  12. E. Boutillon, A. Gazel, J.L. Danger, G. Gulak, H. Laamari, " Un générateur de bruit blanc gaussien sur un FPGA pour la simulation rapide de systèmes de transmissions", 14ième Colloque du GRETSI, Toulouse Sept. 2001
  13. E. Boutillon, W.J., Gross, G. Gulak, " Gestion de la mémoire pour l'algorithme du Forward-Backward", Conférence AAA'2000, Rocquencourt Jan. 2000
  14. L. Gonzalez Perez, E. Boutillon, "Architecture VLSI pour le codage source-canal conjoint en treillis", Conférence AAA'2000, Rocquencourt Jan. 2000
  15. E. Boutillon, J.L Danger, "Implementation d'un demodulateur sur FPGA", Gretsi'97, Grenoble sept. 97.
  16. C. Verdier, A. Lafage, E. Boutillon, A. Demeure, "Un réseau d'alignement Multi-Dimensionnel pour une Architecture SIMD", Actes des Journées des Jeunes Chercheurs en Architectures de Machines, Rennes, décembre 1993.
  17. E. Boutillon, "Pre-etude d'un decodeur de Viterbi", Telecom Paris 92 D 013, Sept 92.
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Patents (Brevets)

  1. E. Boutillon, O. Abassi, L. Conde-Canencia, “Procédé de transmission de mots de code correcteur d'erreur non binaire avec modulation CCSK, signal et dispositif correspondant“, Demande de brevet Français n°1251334, 13 février 2012.
  2. C. Marchand, E. Boutillon, “Low-density parity check code”, European patent application n°10290645.0, December 2010.
  3. E. Boutillon, L. Conde-Canencia, “Procédé de commande d’une unité de calcul, tel qu’un nœud de parité élémentaire dans un décodeur de code LDPC non binaire, et unité de calcul correspondante”, Demande de brevet Français n°FR0952988, 5 may 2009.
  4. M. Ciesielski, S. Askar, E. Boutillon, Jérémie Guillot, “Behavioral transformation for hardware synthesis and code optimization based on Taylor Expansion Diagrams”, United States Patent No. 7,472,359, Dec. 30, 2008. (deposal n°11/292,493, dec. 02, 2005).
  5. E. Boutillon, J. Tousch, F. Guilloud, "LDPC decoder, corresponding method, system and computer programm", United States Patent n°7174495, Feb. 6, 2007 (deposal n°10/742,643, dec. 19, 2003).
  6. E. Boutillon, V. Gaudet, G. Gulak, D. Gnaedig, "Procédé de codage et/ou décodage de codes correcteurs d'erreurs, dispositifs et systèmes correspondants", brevet n° 02 04764, avril 2002.
  7. P. Morreau, L. Fonseca, M. Muller, R. Vallet, E. Boutillon, "Récepteur radio-fréquence pour la télé-relève de compteurs et méthodes de télé-relève de compteurs comprenant un tel récepteur." Brevet n° 001 7075, 22 décembre 2000.
  8. A. Lafage, F. Jutand. E. Boutillon, "Calcul vectoriel à l'intérieur d'un circuit", Brevet numéro 90 07164, Juin 1990.
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PhD report (Rapport de thèse)

  1. E. Boutillon, "Architectures VLSI pour les Transmissions Numeriques dans le Canal de Rayleigh" (in French), Thèse de Doctorat ENST, le 19 décembre 1995.
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