A more recent picture
Professor at UBS
(Universite de Bretagne Sud), Lorient, France,
in the lab Lab-STICC (UMR 6285).
Lab-STICC - Centre de recherche
Université de Bretagne Sud
56325 Lorient Cedex
Tel: (+) 2 97 87 45 66
Secretary: (+) 2 97 87 45 60
Fax: (+) 2 97 87 45 27
- LICENCE 1 SPI (Science Physique de l'Ingénieur): From analog to digital
- LICENCE 2 SPI (Science Physique de l'Ingénieur): Mathematics, Boolean and sequential logic
- LICENCE 3 GEII: Electronics
- MASTER 1 GEII : Linear control (state models), theory of random signal, FPGA, VHDL
- MASTER 2 GEII : Signal processing, Linear control (state models), theory of random signal
- MASTER GEII for people of South America (WEB site)
- 2011: I made a one year sabbatical stay in the INICTEL-UNI, Peru
- Since Sept 2000: Professor at UBS (Lab-STICC)
- 1997-2000: Assistant professor ("Maitre de Conférences") in the department COMELEC
of Telecom ParisTech (Paris, France).
1997-98: I made a one year sabbatical stay in the Department of Electrical and Computer Engineering at the University of Toronto (from August 98 to July 99), working, with professor Glenn Gulak, on VLSI architectures for communication systems.
1996: I worked six months in the Philips research laboratory of Paris
(LEP: Laboratoire d'Electronique de Philips, Limeil Brevannes, France)
on the developement of a real time MPEG-2 encoder circuit.
1992-1995: I worked as a research engineer in the electronic departement
(ELEC) of ENST.
1993-1995: Ph D thesis while working as a research engineer in ENST.
1990-1992: I worked as a professor in a telecommunication school of West
Africa (ESMT: Ecole Superieure Multinationale des Telecommunications) in
1986-1990: Undergraduate studies at Telecom ParisTEch (former ENST).
- Hassan Hard, "hardware implementation of Non-Binary LDPC codes", PhD started in february 2016 (with prof. A. Al Ghouwayel, University Libanaise)
- Franklin Cochachin, "Noised enhanced LDPC and Turbo decoder", PhD started in february 2016 (with prof. D. Declercq, University of Cergy Pontoise)
- Mourad Hafidi, "GPS on stochastic architecture", PhD started in october 2014.
- Ahmed Ahmed Abdmoulah, "Non-binary LDPC codes associated to high-order modulations", PhD started in october 2013.
- Oussama Abassi (june 2014), "Etude des décodeurs LDPC non-binaires",
(PhD report (2.5 Mo))
- Arnaud Dion (december 2012), "Récepteur de navigation reconfigurable pour applications spatiales",
(PhD report (2.2 Mo))
- Yangyang Tang (january 2013), "Computation on Unreliable Architecture"
(PhD report (6.5 Mo))
- Cedric Marchand (janvier 2010), "Implementation of an LDPC decoder for the
DVB-S2, -T2 and -C2 standards", PHd with NXP (PhD report (4.8 Mo)
- Aswhani Singh (december 2009), "Flexible turbo/ldpc decoders", PHd with Guido Masera (Politecnico de Torino), (PhD report (4.4 Mo))
- Sébastien Trégaro (July 2009), "Détection et estimation de signaux radars", PHd with RUBISOFT
- Haisheng Liu (July 2009), "Contributions à la maîtrise de la consommation dans
des turbo-décodeurs", PHd with ENST-Bretagne, (PhD report (3.4 Mo))
- Jeremie Guillot (Sept. 2008), "Optimization Techniques for
High Level Synthesis and pre-Compilation based on Taylor Expansion Diagrams",
joint project with Prof. M. Ciesielski, (PhD report (4.7 Mo))
- Amor Nafkha, (march 2006), "Architecture MIMO", PHd, PALMYRE PROJECT (PhD report (2.4 Mo))
- Pierre Bomel ,
, "Automatic implementation of GALS", PHd PALMYRE PROJECT.
(PhD report (1.9 Mo))
- David Gnaedig, "Turbo-Codes à roulettes", PHd with Turbo-Concept
company.(PhD report (2.8 Mo))
- Frederic Guilloud, "Architecture générique de décodeur de codes LDPC" (PhD report (2.6 Mo))
Gay-Bellile , "Programmable architecture for channel decoding"
(abstract), (PhD report (1.2 Mo))
Gonzalez, "VLSI architecture for combined source-channel coding"
(abstract), (PhD report (1.6 Mo))
Research and interest
My research area is in VLSI architectures and communications.
Current research areas:
- Noise Against Noise Decoder (an ANR funded grant) (more information in NAND project).
- Non binary LDPC codes: (more information in Current project, or in DaVinci project (FP7)
- High speed time synchronization (more information in High speed Gardner algorithm).
- Computation on unreliable architecture (more information in Unreliable Architecture project).
- Low Density Parity Check code: (more information in LDPC project).
Previous research areas:
- Trellis aggregation for high code rate turbo-code (more information in trellis aggregation).
- Turbo-Code architecture
- 8PSK demodulation: (more information in 8PSK project).
- Taylor Expansion Diagrams: (more information
in TED project).
- Hardware correlator: (more information
in Hardware correlator project).
- Generic MIMO decoder: (more information
in Generic MIMO decoder project).
- (2001-2006) Slice Turbo Code: (more information
in Slice Turbo Code project).
- (2000-2002) White Gaussian Noise Generator for channel emulation (more information
in WGNG project).
- (1999-2001) Forward-Backward (or MAP, BJCR) project: this project deals on the construction of an WEB site
dedicated to VLSI for MAP algorithm. Some datas are presently available
- (1995-1999) Auger Project: During the 3 last years, I have also been involved in the design of the
telecommunication network of the international
PROJECT (two 3000 km2 giant cosmic rays detector).
- Decoding architecture for Cortex code (2011-2014)
- Demodulateur architecture and LDPC decoder architecture for DVB-S2 standard (2009-2011, 2013-2014)
- ELINT systems(2005).
- Slice Turbo Code (since 2001).
- Specification and hardware realization of a family of digital demodulator for
a radio application (1996-1999).
- Soft Reed-Solomon decoder (1998).
- Realisation of a real time "smart" Variable Length Coding for an MPEG-2
- First generation of a digital demodulator with a CLP ( FLEX10K50)
- Realisation in standard cell (VHDL synthesis) of a real time DCT-IDCT for an MPEG-2 encoder (20 K gates, 27 MHz, precision compatible with the MPEG-2 standard) (1995).
- Work with the team that has defined the Array-Ol formalizen to describe array signal processing (1993 - 1994).
- Architecture study for an 30 MHz viterbi decoder for a 4 Dimentional TCM
Go here for the list of publications of 2012 and later
Go here for the list of publications before 2012
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