Emmanuel Boutillon

 


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Professor at UBS (Universite de Bretagne Sud), Lorient, France, in the lab Lab-STICC (UMR 6285).

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Teaching

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Work experience

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PhD students

Current PhD-Students:
  1. Hassan Hard, "hardware implementation of Non-Binary LDPC codes", PhD started in february 2016 (with prof. A. Al Ghouwayel, University Libanaise)
  2. Franklin Cochachin, "Noised enhanced LDPC and Turbo decoder", PhD started in february 2016 (with prof. D. Declercq, University of Cergy Pontoise)
  3. Mourad Hafidi, "GPS on stochastic architecture", PhD started in october 2014.
  4. Ahmed Ahmed Abdmoulah, "Non-binary LDPC codes associated to high-order modulations", PhD started in october 2013.

Former PhD-Students:

  1. Oussama Abassi (june 2014), "Etude des décodeurs LDPC non-binaires", (PhD report (2.5 Mo))
  2. Arnaud Dion (december 2012), "Récepteur de navigation reconfigurable pour applications spatiales", (PhD report (2.2 Mo))
  3. Yangyang Tang (january 2013), "Computation on Unreliable Architecture" (PhD report (6.5 Mo))
  4. Cedric Marchand (janvier 2010), "Implementation of an LDPC decoder for the DVB-S2, -T2 and -C2 standards", PHd with NXP (PhD report (4.8 Mo)
  5. Aswhani Singh (december 2009), "Flexible turbo/ldpc decoders", PHd with Guido Masera (Politecnico de Torino), (PhD report (4.4 Mo))
  6. Sébastien Trégaro (July 2009), "Détection et estimation de signaux radars", PHd with RUBISOFT
  7. Haisheng Liu (July 2009), "Contributions à la maîtrise de la consommation dans des turbo-décodeurs", PHd with ENST-Bretagne, (PhD report (3.4 Mo))
  8. Jeremie Guillot (Sept. 2008), "Optimization Techniques for High Level Synthesis and pre-Compilation based on Taylor Expansion Diagrams", joint project with Prof. M. Ciesielski, (PhD report (4.7 Mo))
  9. Amor Nafkha, (march 2006), "Architecture MIMO", PHd, PALMYRE PROJECT (PhD report (2.4 Mo))
  10. Pierre Bomel , , "Automatic implementation of GALS", PHd PALMYRE PROJECT. (PhD report (1.9 Mo))
  11. David Gnaedig, "Turbo-Codes à roulettes", PHd with Turbo-Concept company.(PhD report (2.8 Mo))
  12. Frederic Guilloud, "Architecture générique de décodeur de codes LDPC" (PhD report (2.6 Mo))
  13. Olivier Gay-Bellile , "Programmable architecture for channel decoding" (abstract), (PhD report (1.2 Mo))
  14. Luis Gonzalez, "VLSI architecture for combined source-channel coding" (abstract), (PhD report (1.6 Mo))

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Research and interest

My research area is in VLSI architectures and communications.

Current research areas:

  1. Noise Against Noise Decoder (an ANR funded grant) (more information in NAND project).
  2. Non binary LDPC codes: (more information in Current project, or in DaVinci project (FP7)
  3. High speed time synchronization (more information in High speed Gardner algorithm).
  4. Computation on unreliable architecture (more information in Unreliable Architecture project).
  5. Low Density Parity Check code: (more information in LDPC project).

Previous research areas:

  1. Trellis aggregation for high code rate turbo-code (more information in trellis aggregation).
  2. Turbo-Code architecture
  3. 8PSK demodulation: (more information in 8PSK project).
  4. Taylor Expansion Diagrams: (more information in TED project).
  5. Hardware correlator: (more information in Hardware correlator project).
  6. Generic MIMO decoder: (more information in Generic MIMO decoder project).
  7. (2001-2006) Slice Turbo Code: (more information in Slice Turbo Code project).
  8. (2000-2002) White Gaussian Noise Generator for channel emulation (more information in WGNG project).
  9. (1999-2001) Forward-Backward (or MAP, BJCR) project: this project deals on the construction of an WEB site dedicated to VLSI for MAP algorithm. Some datas are presently available (FORWARD-BACKWARD ARCHITECTURE).
  10. (1995-1999) Auger Project: During the 3 last years, I have also been involved in the design of the telecommunication network of the international AUGER PROJECT (two 3000 km2 giant cosmic rays detector).

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Industry collaborations

  1. Decoding architecture for Cortex code (2011-2014)
  2. Demodulateur architecture and LDPC decoder architecture for DVB-S2 standard (2009-2011, 2013-2014)
  3. ELINT systems(2005).
  4. Slice Turbo Code (since 2001).
  5. Specification and hardware realization of a family of digital demodulator for a radio application (1996-1999).
  6. Soft Reed-Solomon decoder (1998).
  7. Realisation of a real time "smart" Variable Length Coding for an MPEG-2 encoder (1997).
  8. First generation of a digital demodulator with a CLP (  FLEX10K50) (1996).
  9. Realisation in standard cell (VHDL synthesis) of a real time DCT-IDCT for an MPEG-2 encoder (20 K gates, 27 MHz, precision compatible with the MPEG-2 standard) (1995).
  10. Work with the team that has defined the Array-Ol formalizen to describe array signal processing (1993 - 1994).
  11. Architecture study for an 30 MHz viterbi decoder for a 4 Dimentional TCM modulation (1992).
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Publications

Go here for the list of publications of 2012 and later

Go here for the list of publications before 2012

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