Key words: VLSI, Architecture, Turbo code, slice, high speed, interleaver
Abstract: The main problem with the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this problem with a new family of turbo codes, called Slice Turbo Codes. This family is based on two ideas: the encoding of each dimension with P independent tail-biting codes and a constrained interleaver structure that allows parallel decoding of the P independent codewords in each dimension. The optimization of the interleaver is described. A high degree of parallelism is obtained with equivalent or better performance than the best known turbo codes. The parallel architecture allows reduced complexity turbo decoding for very high throughput applications.
Full Paper of the confence: Click Here
Paper submitted to the "Annal of telecommunication", special issue on the 3rd International Symposium on Turbo Codes and Related Topics: Click Here Poster of the paper: Click HereAuthors: David Gnaedig, Emmanuel Boutillon, Michel Jezequel, Vincent C. Gaudet and P. Glenn Gulak
Reference: Proceedings of the 3nd International Symposium on Turbo Codes & Related Topics, Brest, France, Sept. 2003.