Key words: VLSI, Architecture, LDPC, Error control coding, Low Density Parity Check Code
Abstract: : The natural approch to design a code is first to find a code, then, define the hardware structure of the decoder. Unfortunately, such a constructed code has very little chance to be suited for a hardware implementation. This paper propose to operate in the other way: In a first step an efficient hardware structure is chosen and in a second step, a code is constructed that adequately fits this structure. An example of such methodology is exposed for a Low Density Parity Check code. A cascadable high speed (clock cycle equal to bit rate) decoder archictecture is presented and simulation results are given. For a N=4096 LDPC code of rate 1/2 gives, a Bit Error Rate of 10-4 is acheived respectively for a SNR of 2.63 dB (1 circuit), 2,3 dB (2 circuits) and 2.05 dB (10 circuits).
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Authors: Emmanuel Boutillon, Jeff Castura, Frank R.Kschischang
Reference: Proceedings of the 2nd International Symposium on Turbo Codes & Related Topics, pp 459-62, Brest, France, Sept. 2000.