Cyrille CHAVET

Université Bretagne Sud

Books

2015

   C. Chavet and P. Coussy Editors
"Advanced Hardware Design for Error Correcting Codes", Springer, ISBN: 978-3-319-10568-0 (Print) / 978-3-319-10569-7 (Online), 2015.

FEC Book C. Chavet, A. Sani and P. Coussy, "Hardware Design of Parallel Interleaver Architectures: A Survey", In Advanced Hardware Design for Error Correcting Codes, pages 177-192, Springer, 2015.

2008

HLS book Philippe Coussy, Cyrille Chavet, Pierre Bomel, Dominique Heller, Eric Senn and Eric Martin, "GAUT: A High-Level Synthesis Tool for DSP Applications", In High level Synthesis: from Algorithm to Digital Circuit, pages 147-169, Springer, june 2008.

Journals

2021

Springer Nature - Jour. Sig. Proc. Sys. H. Harb and C. Chavet, "Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards", (Springer Nature) Journal of Signal Processing Systems, (), 1-8, 2021, Digital Object Identifier: 10.1007/s11265-020-01628-w

2020

IEEE Trans. CAS II H. Harb and C. Chavet, "Fully Parallel Circular-Shift Rotation Network for Communication Standards", IEEE Transactions on Circuits and Systems--II: Express Briefs, (Volume 67, Issue 12, 2020, pages 3412-3416) Digital Object Identifier: 10.1109/TCSII.2020.2997691.

2019

IEEE Trans. NNLS H. Nono Wouafo, C. Chavet and P. Coussy, "Clone-Based Encoded Neural Networks to Design Efficient Associative Memories", IEEE Transactions on Neural Networks and Learning Systems, Print ISSN: 2162-237X (Volume 30, Issue 10, October 2019, pages 3186 - 3199), Online ISSN: 2162-2388, Digital Object Identifier: 10.1109/TNNLS.2018.2890658.

2015

ACM JeTC P. Coussy, C. Chavet, L. Conde-Canencia and H. Nono Wouafo,"Fully-Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories", ACM Journal on Emerging Technologies in Computing Systems, Special issue, Vol 11, Issue: 4, April 2015.

2013


IEEE Trans. Signal Proc. A.H. Sani, S. Ur Reehman, C. Chavet and P. Coussy, "A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm", IEEE Transactions on Signal Processing, Vol 61 - 2013, Issue: 16, pp. 4127-4140.


T.S.I. V. Lapotre, P. Coussy and C. Chavet, "Introduction de la prédiction de branchement dans la synthèse de haut niveau", Revue des sciences et technologies de l'information, Architectures des ordinateurs, Vol 32/2 - 2013, pp.281-301, Selected paper.

2010

IEEE Trans. CAD C. Andriamisaina, P. Coussy, E. Casseau and C. Chavet, "High-Level Synthesis for Designing Multimode Architectures", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 29, Issue:11, page 1736-1749, november 2010.

Patents

2014

Int. patent Cyrille Chavet, Philippe Coussy and Nicolas Charpentier, "NEURAL NETWORK ARCHITECTURE, PRODUCTION METHOD, AND PROGRAMMES CORRESPONDING THERETO", Patent no. WO/2014/079990

2013

FR & EU patent Cyrille Chavet, Philippe Coussy, "Dispositif auto-configurable d'entrelacement/désentrelacement de trames de données", Patent no. FR12.51688.

2012

FR & EU patent Cyrille Chavet, Philippe Coussy and Nicolas Charpentier, "Architecture de réseau de neurones, procédé d'obtention et programmes correspondants.", Patent no. FR12.61155

FR & EU patent John Shield, Jean-Philippe Diguet, Philippe Coussy and Cyrille Chavet, "Système de traitement de données avec cache actif", Patent no. FR12.56715

2009

US patent Cyrille Chavet, Philippe Coussy, Eric Martin and Pascal Urard, "Apparatus for data interleaving algorithm", Patent no.20090031094

2007

FR & EU patent Cyrille Chavet, Philippe Coussy, Eric Martin and Pascal Urard, "Apparatus for data interleaving algorithm", Patent no. FR0754793

Internationnal conferences

2021

5G WF M. Tourres, C. Chavet, B. Le Gal, J. Crenne and P. Coussy, "Extended RISC-V hardware architecture for future digital communication systems," 2021 IEEE 4th 5G World Forum (5GWF), 2021, pp. 224-229, doi: 10.1109/5GWF52925.2021.00046

2020

ICASSP H. Harb and C. Chavet, "Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards", In Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), page XX-YY, Barcelonne, May 2020

ISCAS G. Harcha, V. Lapôtre, C. Chavet and P. Coussy, "Toward secured iot devices: A shuffled 8-bit AES hardware implementation", In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2020

2019

ICASSP C. Chavet, F. Lozachmeur, T. Barguil, A. Sani and P. Coussy, "Solving Memory Access Conflicts in LTE-4G Standard", In Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), page XX-YY, Brighton, May 2019

2017

SiPS H. Nono Wouafo, C. Chavet, R. Danilo and P. Coussy, "Efficient Scalable Hardware Architecture for Highly Performant Encoded Neural Networks", In Proceedings of IEEE International Workshop on Signal Processing Systems, SiPS, page XX-YY, Lorient, France, October 2017

2016

DASIP R. Danilo, H. Nono Wouafo, C. Chavet and P. Coussy, "Associative memory based on clustered neural networks: improved model and architecture for oriented edge detection", In Proceedings of Conference on Design & Architectures for Signal & Image Processing, DASIP, page XX-YY, Rennes, France, October 2016

DATE P. Coussy, C. Chavet and A. Sani, "A Dynamically Reconfigurable ECC Decoder Architecture", In Proceedings of DATE 2016, page XX-YY, Dresden, march 2016

WInnComm-Europe C. Chavet and P. Coussy, "A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond)", In Wireless Innovation Forum European Conference on Communications Technologies and Software Defined Radio 2016, page XX-YY, Paris, october 2016

2015

DATE S. Ur Rehman, C. Chavet and P. Coussy, "In-place memory mapping approach for optimized parallel hardware interleaver architectures", In Proceedings of DATE 2015, page XX-YY, Grenoble, France, march 2015

DATE - Neural Coding workshop H. Nono Wouafo, C. Chavet and P. Coussy, "Improving Storage of Patterns in Binary Cluster-Based Neural Networks: Clone-based Model and Architecture", In second internationnal workshop on Neural Coding, co-located with DATE Conference 2015, Grenoble, France, march 2015

ISCAS H. Nono Wouafo, C. Chavet and P. Coussy, "Improving Storage of Patterns in Recurrent Neural Networks: Clones Based Model and Architecture", In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2015, page XX-YY, Lisbonne, Portugal, may 2015.

2014

GLSVLSI S. Ur Rehman, C. Chavet and P. Coussy, "A Memory Mapping Approach based on Network Customization to Design Conflict-Free Parallel Hardware Architectures", In Proceedings of the 24th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2014, page XX-YY, Houston, Texas, USA, may 2014

ICASSP S. Ur Rehman, A. Sani, P. Coussy and C. Chavet, "Embedding Polynomial Time Memory Mapping and Routing Algorithms on-chip to Design Configurable Decoder Architecture", In Proceedings of the 39th IEEE International Conference on Acoustics, Speech and Signal Processing, Florence, Italy, May, 2014.

SB-VLSI - Invited talk J.P. Diguet, P. Coussy, and C. Chavet, "VLSI Architectures and NoCs for Neural Coding", In 1st International Symposium on Brainware LSI, Mar 2014,Japan.

ICECS M. Lanoe, M. Bordin, D. Heller, P. Coussy and C. Chavet, "A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code", In Proceedings of the 21st IEEE International Conference on Electronics Circuits & Systems, Marseille, France, December, 2014.

2013

FPL V. Lapotre, P. Coussy, C. Chavet, H. Wouafo and R. Danilo, "Dynamic Branch Prediction For High-Level Synthesis", In Proceedings of International Conference on Field Programmable Logic and Applications (FPL) 2013, page XX-YY, Porto, Portugal, sept. 2013

GLSVLSI A. Briki, C. Chavet and P. Coussy, "A Memory Mapping Approach for Network and Controller Optimization in Parallel Interleaver Architectures", In Proceedings of the 23th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2013, page XX-YY, Paris, France, may 2013

DATE - Neural Coding workshop H. Nono Wouafo, C. Chavet, P. Coussy and L. Conde-Canencia, "Neuromorphic Hardware Architectures: Toward a Binary GBNN Neural Network Model", In Frist internationnal workshop on Neural Coding, co-located with DATE Conference 2013, Grenoble, France, march 2013

SiPS A. Briki, C. Chavet and P. Coussy, "A Conflict-Free Memory Mapping Approach To Design Parallel Hardware Interleaver Architectures With Optimized Network And Controller", In Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), page XX-YY, Taipei : Taiwan, Province De Chine, oct. 2013

ICASSP S. Ur Rehman, A. Sani, P. Coussy and C. Chavet, "On-Chip Implementation Of Memory Mapping Algorithm To Support Flexible Decoder Architecture", In Proceedings of the 38th IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, May, 2013.

2012

GLSVLSI A. Briki, C. Chavet, P. Coussy and E. Martin, "A Design Approach Dedicated to Network-Based and Conflict-Free Parallel Interleavers", In Proceedings of the 22th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2012, page XXX, Salt lake City, USA, may 2012

DSD P. Burgio, A. Marongiu, D. Heller, C. Chavet, P. Coussy, and L. Benini, "OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters", In Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods & Tools, page XXX, Cesme, Izmir, Turkey, September 5-8, 2012

SIPS O. Sanchez, S. ur Rehman, A. Sani, C. Jego, C. Chavet, P. Coussy, and M. Jezequel, "A dedicated approach to explore design space for hardware architecture of turbo decoders", In Proceedings of the IEEE Workshop on Signal Processing Systems, page XXX, Quebec, Canada, October 17-19, 2012

2011

ASICON - Invited paper P. Coussy, D. Heller, and C. Chavet, "High-Level Synthesis: On the Path to ESL Design", In Proceedings of the 9th International Conference on ASIC (ASICON 2011), Xiamen, China.

ISCAS A. H. Sani, P. Coussy, C. Chavet, and E. Martin, "An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture", In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2011, page XX-YY, Rio de Janeiro, Brazil, may 2011. Selection for student paper contest

ICASSP A. H. Sani, P. Coussy, C. Chavet, and E. Martin, "A Methodology based on Transportation Problem Modeling for Designing Parallel Interleaver Architectures", In Proceedings of the 36th IEEE International Conference on Acoustics, Speech and Signal Processing, Prague, May 22-27, 2011.

2010

ICECS A. H. Sani, P. Coussy, C. Chavet, and E. Martin, "Design Of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach", In procedings of the IEEE International Conference on Electronics, Circuits, and Systems, Athens, Greece (ICECS) 2010, page. XX-YY, december 2010

ISCAS C. Chavet and P. Coussy, "A memory Mapping Approach for Parallel Interleaver design with multiples read and write accesses", In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2010, page 3168-3171, Paris, France, june 2010

ICASSP C. Chavet, P. Coussy, E. Martin and P. Urard, "Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures", In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2010, page 1594-1597, Dallas, Etats-Unis, march 2010
Also here : NASA

2008

DATE C. Chavet, P. Coussy, E. Martin, and P. Urard, "Design space exploration tool for Space-Time AdapteRs", Workshop The new wave of High Level Synthesis, in Design, Automation and Test in Europe (DATE) 2008, Munich, Allemagne, march 2008

DATE C. Chavet, P. Coussy, E. Martin, and P. Urard, "Design Methodology for Efficient Space Time AdapteR", PhD forum, in Design, Automation and Test in Europe (DATE) 2008, Munich, Allemagne, march 2008

2007

ICCAD C. Chavet, C. Andriamisaina, P. Coussy, E. Casseau, E.Juin, P. Urard, and E. Martin, "A Design Flow Dedicated to Multi-mode Architectures for DSP Applications", In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD) 2007, pages 604-611, San Jose, USA, november 2007

EUSIPCO C. Chavet, P. Coussy, P. Urard, and E. Martin, "Application of a design space exploration tool to enhance interleaver generation", In Proceedings of the European Signal Processing Conference (EUSIPCO) 2007, page XX-YY, Poznan, Pologne, september 2007.

ISCAS C. Chavet, P. Coussy, P. Urard, and E. Martin, "A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver", In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2007, page 2946, New Orleans, Etats-Unis, may 2007.

GLSVLSI C. Chavet, P. Coussy, P. Urard, and E. Martin, "A Design Methodology for Space-Time Adapter", In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2007, page 347, Stresa, Italie, march 2007

2006

FDL - Invited paper C. Chavet, "Moving to System Level Design Requierements & Challenges", In Forum on specification & Design Languages (FDL) 2006, Darmstadt, Allemagne, september 2006

Nationnal conferences

2021

COMPAS M. Tourres, B. Le Gal, J. Crenne, C. Chavet and P. Coussy, "Architecture matérielle programmable optimisée pour les systèmes de communications numériques", In Conférence francophone d'informatique en Parallélisme, Architecture et Système, 6-9 juillet 2021, Lyon

GDR SoC2 Tourres, M., Legal, B.,Chavet,C., Crenne, J., and Coussy, P., "Architecture programmable pour les systèmes de communications numériques.", In Conférence annuel du GDR SoC2, Rennes, France.

2016

GDR SoC-SiP H. Wouafo, C. Chavet and P. Coussy, "Amélioration des performances des mémoires associatives par les réseaux à clones", In Colloque National du GDR SoC-SiP, Nantes, France, june 2016.

2015

GRETSI H. Nono Wouafo, C. Chavet and P. Coussy, "Modèle et Architecture de Réseaux de Neurones Récurrents à Clones", In Colloque National du GRETSI, Lyon, France, september 2015.

2014

Journée Bio-mimétisme Invited talk C. Chavet and P. Coussy, "Modélisation de la vision inspirée du vivant", Journée prospective: Innover par la voie du biomimétisme, Organisée par Images et Réseaux, EMC2, iD4CAR, le Comité 21 et le cluster Eco-origin, Invited talk, Rennes, Oct. 2014.

GDR SoC-SiP S. Ur Rehman, C. Chavet and P. Coussy, "Designing optimized parallel interleaver architecture through network customization", In Colloque National du GDR SoC-SiP, Paris, France, june 2014.

2013

GRETSI A. Briki, C. Chavet, P. Coussy and E. Martin, "Placement de données en mémoire sans conflit pour l´optimisation du réseau d´interconnexion et du contrôleur des entrelaceurs parallèles", In Colloque National du GRETSI, Brest, France, september 2013.

2012

GDR SoC-SiP A. Briki, P. Coussy, C. Chavet, and E. Martin, "A Design Approach Dedicated to Pattern-Based and Conflict-Free Parallel Memory Systems", In Colloque National du GDR SoC-SiP, Paris, France, june 2012.

2011

SYMPA V. Lapotre, P. Coussy, C. Chavet, "Prédiction de Branchement dans la Synthèse de Haut Niveau", In SYMPosium en Architectures, Saint Malo, Mai 2011.
Selected paper for journal publication

GDR SoC-SiP a. Briki, P. Coussy, C. Chavet, and E. Martin, "A Design Approach Dedicated to Pattern-Based and Conflict-Free Parallel Memory System", In Colloque National du GDR SoC-SiP, Lyon, France, june 2011.

GDR SoC-SiP A. H. Sani, P. Coussy, C. Chavet, and E. Martin, "Designing Parallel Interleaver architecture through Tripartite Edge Coloring Approach", In Colloque National du GDR SoC-SiP, Lyon, France, june 2011.

2010

GDR SoC-SiP A. H. Sani, P. Coussy, C. Chavet, and E. Martin, "A Bipartite Edge Coloring Approach for designing Parallel Interleaver architecture", In Colloque National du GDR SoC-SiP, Paris, France, june 2010.

2007

GRETSI C. Chavet, P. Coussy, E. Martin, and P. Urard, "Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels", In Colloque National du GRETSI, Troyes, France, september 2007.

GDR SoC-SiP C. Chavet, P. Coussy, E. Martin, and P. Urard, "Méthodologie de synthèse d'adaptateurs spatio-temporels", In Colloque National du GDR SoC-SiP, Paris, France, june 2007.

2005

MajecSTIC C. Chavet, P. Coussy, E. Martin, and P. Urard, "Approche formelle pour la conception d'adaptateurs spatio-temporels", In Conférence MajecSTIC (Manifestation des jeunes chercheurs an STIC), Rennes, France, november, 2007.