Chavet

Research interrests

Computer Aided Design & High Level Synthesis

Architectures and Compilers for Embedded Systems

Conflict-free and in-place memory mapping

Software/Hardware synthesis, analysis and verification

Advanced architecture for Neural Networks and Associated Design Tools

Architecture for post-quantic cryptography

PhD thesis proposal

Advanced architecture and post-quantic cryptography

RISC-V / Architecture / Error Correction Codes
Improving RISC-V Instruction Set Architecture with ECC optimized instructions

Publications:
IEEE 5G world Forum 2021
Director: Philippe Coussy
Co-Supervisor: Bertrand Legal
Duration:

Collaborations and Post-Doc

Hassan Harb

Interleaver design

Publications:
Jour. Signal Processing 2021 (Springer-Verlag/Nature)
IEEE Trans. CAS II 2020
ICASSP 2020
Project FlexDEC-5G
Co-Supervisor: Philippe Coussy
Duration: 2017 - 2020

Paolo Burgio

High Level Synthesis

Publications:
DSD 2012
Director: Luca Benini
Co-Supervisor: Philippe Coussy
Duration: 2011 - 2014

Oscar

Memory mapping

Publications:
SiPS 2012
Director: Michel Jezequel
Duration: 2019 - 2012

Alumni

Ghita Harcha

Security / Architecture / Encryption
Integrated Hardware Architecture and Sparse Neural Network Models

Publications:
ISCAS 2020
Director: Philippe Coussy
Co-Supervisor: Vianney Lapôtre
Duration: 2017 - 2021 (Defense: early july 2020)

Huges Nono Wafo

Neural Network Architecture
Integrated Hardware Architecture and Sparse Neural Network Models

Publications:
SiPS 2017
DASIP 2016
GDR SoC-SiP 2016
Journal Paper 2015 - JeTC
ISCAS 2015
DATE 2013 - NeuComp workshop
Director: Philippe Coussy
Co-Supervisor:
Duration: 2012 - 2015 (Defense: early january 2016)

Saeed Ur Rehman

High Level Synthesis
Conflict-free memory mapping and advanced architectural model

Publications:
DATE 2015
GLS-VLSI 2014
ICASSP 2014
ICASSP 2013
SiPS 2012
Director: Philippe Coussy and Michel Jezequel
Co-Supervisor:
Duration: 2011 - 2014 (Defense: september 2014)

Aroua Briki

High Level Synthesis
Conflict-free memory mapping

Publications:
SiPS 2013
GLS-VLSI 2013
GRETSI 2013
GLS-VLSI 2012
GdR SoC-SiP 2012
GdR SoC-SiP 2011
Director: Eric Martin
Co-Supervisor: Philippe Coussy
Duration: 2009 - 2013 (Defense: june 2013)

Sani Awais Hussein

High Level Synthesis
Bipartite edge coloring

Publications:
DATE 2016
IEEE Trans. on Signal Processing 2013
ICASSP 2013
ICASSP 2011
ISCAS 2011
ICECS 2010
GdR SoC-SiP 2011
GdR SoC-SiP 2010
Director: Eric Martin
Co-Supervisor: Philippe Coussy
Duration: 2008 - 2011 (Defense: may 2012)

Projects

FlexDEC-5G Project

FEDER project

The project aims at developing a flexible architecture of channel code decoding for the 5G networks (wireless broadband, IoT, M2M).
Duration: 2017 - 2019

Publications:
IEEE ICASSP 2020
IEEE ICASSP 2019
WinnComm-Europe 2016

Human Brain Project Project

European Flagships project

The Human Brain Project should lay the technical foundations for a new model of ICT-based brain research, driving integration between data and knowledge from different disciplines, and catalysing a community effort to achieve a new understanding of the brain, new treatments for brain disease and new brain-like computing technologies.
Duration: 2012 - 2022

HiPEAC Project

European Network of Excellence on High Performance and Embedded Architecture and Compilation
Funded under 7th FWP (EU Seventh Framework Programme, FP7).
Duration: 2010 - 2014

Main contribution:

HiPEAC 2012 / Paris / Co-Organizor of the industrial exhibits and poster sessions

HiPEAC 2013 / Berlin / Co-Organizor of the workshop "High-Level Synthesis for High Performance Computing"

SENSE Labex CominLabs' Project

Academic Partners: UBS-LabSTICC, Telecom Bretagne-Lab-STICC, UBS-IRISA

The SENSE project is a Labex CominLabs' project that gathers academic partners in order to develop the next-generation artificial vision system inspired from biological eyes.

The main goals are the following:

to define a the futur architectural model

to propose industrial quality prototype

Duration: October 2013 - October 2016

GRAAL SATT Ouest Valorisation & Lab-STICC Project

The GRAAL project is a project dedicated construct an idustrial demonstrator for a technology proposed on one of our patents.

The main goals are the following:

to propose industrial quality prototype

Duration: july 2013 - july 2014

GigaDEC Project

Industrial Partners: Turbo-Concept
Academic Partners: Telecom Bretagne-Lab-STICC, UBO, UBS-LabSTICC

The GigaDEC project is a French project that gathers industrial and academic partners in order to develop the next-generation of very high throughput (Giga) signal coder/decoder (DEC).

The main goals are the following:

to define a the futur architectural model

to propose industrial quality prototype

to reduce design time (by exploring no design concepts)

Duration: October 2011 - October 2013

P Project

Industrial Partners: Continental, AdaCore, Airbus, Astrium, Rockwell Collins, Sagem, Thales Avionics, Aboard,Thales Alenia Space, Atos, ACG Solutions, Altair, Scilab, STI, ONERA
Academic Partners: UPS-IRIT, UBS-LabSTICC, INRIA, ENPC

The P project is a French project that gathers industrial and academic partners from the Aerospace Valley and Systematic pôles to address the issue of Model-Driven design methodologies for critical embedded systems.

The main goals are the following:

to define a formal model "P" that could be the unique model to describe/transform an application from many formal approaches (UML, MathLab, SciLab...) to any decription (C code, VHDL or SystemC architectures...)

to apply these methodologies to critical embedded systems

to reduce design time (by enabling concurrent hardware and software development)

Duration: 2011 - 2014

SoCKET Project

Industrial Partners: Airbus, Astrium, CNES, STMicroelectronics, Thales R&T, Schneider Electric Industries, PSI-S, CEA-LETI, Magilem Design Services
Academic Partners: INPG-TIMA, UPS-IRIT, UBS-LabSTICC

The SoCKET project (SoC toolKit for critical Embedded sysTems) is a French project that gathers industrial and academic partners from the Aerospace Valley and Minalogic pôles to address the issue of design methodologies for critical embedded systems.

The main goals are the following:

to define a "seamless" design flow which integrates qualification and certification, from the system level to integrated circuits and to software

to apply the SoC's design methodologies to critical embedded systems

to reduce design time (by enabling concurrent hardware and software development) and to optimize SoC-based design

to disseminate these methodologies through the Aerospace Valley and Minalogic pôles

Duration: June 2008 - December 2011

High Level Synthesis

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior [HLS]. The starting point of a high-level synthesis flow is ANSI C/C++/SystemC code. The code is analyzed, architecturally constrained, and scheduled to create a register transfer level hardware design language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation. Verification of the RTL is an important part of the process [EE Times].