Johann Laurent, Associate Professor

Lab-STICC Laboratory

Université Européenne de Bretagne-UBS

CNRS- UMR 6285

Centre de recherche - BP92116 - 56321 Lorient Cedex, France

Phone: +33 (0)2 97 87 45 63

Fax: +33 (0)2 97 87 45 27

email: johann.laurent@univ-ubs.fr

Secretary of the Lab-STICC (Florence Palin): +33 (0)2 97 87 45 60

Master in Electronic & Informatic - UBS University

I obtained my PhD in Electronic in 2002 at the Université de Bretagne Sud (UBS) - Lorient, France

- Advisor: Pr Eric Martin
- Subject: Consumption Estimation at System Level Design for Real Time Embedded Applications (French Version only)

Research

My research activities deals mainly with:

Power Energy Consumption Estimation of Hardware & software parts for System on Chip (SoC)

Development of Power Models for processors (GPP - DSP)

Design of Power/Energy Consumption Tool: SoftExplorer

Development of Power Models for hardware (IPs implented on FPGA)
Development of Power Models for SoC interconnects: Antoine Courtay PhD Student

Design of Optimization Technique (Patented technique)
Design of Power/Energy Estimation Tool for interconnects: InterconnectExplorer

Critical Embedded Systems Consumption Modelization

Integration of Multi-Level Power Models in the Archietcure Analysis & Design Language (AADL) Flow

SPICES European ITEA Project support this research

Development of Power Models for Real Time Operating Systems (RTOS)
Development of Power Models for System Peripherals (Ethernet, CAN, Video Controler...)

Memory Mapping Impact Modelization

Development of Methodology for Optimizing the Data Placement into Memory

Design of an Automatic Tool generating the Optimum Data Placement of an Application (from the C code): MemExplorer

Publication

List of publications

Teaching

My teaching activities are realized in the Electronique et Informatique Industrielle (EII) Departement of the Université de Bretagne Sud (UBS)

LICENCE EII

Linear Control
Microprocessor Architecture (Moore & Mealy machines, Von Neumann Model, Cache Memory, Memory Management...)

Course, tutorials and practicals

Electro Magnetism Compatibility (CEM)
Technical Project based on Microcontroller development board

MASTER 1 EII

Advanced Architecture (SuperScalar & VLIW Architecture...)

Course, tutorials and practicals

Computer Aide Design (VHDL language)
Technical Project based on FPGA Development Board

Use of Xilinx Tool (ISE Fundation)

Analog Transmission (AM, FM)

MASTER 2 EII

Management of the MASTER 2 (professional )
Technical Project

Project whom the aim is to develop from specifications a whole system (technical study

Management of MASTER EII-SIAM

Master1 EII-SIAM

List of Master1 Courses
List of last Training Positions :
List of Projects:
List of Training Positions : Training Preiod Sarting Date 02nd of April 2012

Master2 EII-SIAM

List of last Training Positions
List of Training Positions :Training Period Starting Date 30th of January 2012