Emmanuel Boutillon
My picture
Professor at the UBS
(Universite de Bretagne Sud), Lorient, France,
in the group LESTER.
Lab-STICC - Centre de recherche
Université de Bretagne Sud
56325 Lorient Cedex
Tel : (+) 2 97 87 45 66
Secretary : (+) 2 97 87 45 60
Fax : (+) 2 97 87 45 27
email : Emmanuel.Boutillon@univ-ubs.fr
Version Francaise

Teaching
- LICENCE 2 GEII : Mathematic
- LICENCE 3 GEII : Electronics
- MASTER 1 GEII : Linear control (state models), theory of random signal, FPGA, VHDL
- MASTER 2 GEII : Signal processingLinear control (state models), theory of random signal
- MASTER RESEARCH electronics

Work experience
- Since Sept 2000 : Professor at UBS (Lab-STICC)
- 1997-2000: Assistant professor ("Maitre de Conférences") in the department COMELEC
of Ecole Nationale Supérieure des Télécommunications (ENST) (Paris, France).
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1997-98: I made a one year sabbatical stay in the Department of Electrical and Computer Engineering at the University of Toronto (from August 98 to July 99), working, with professor Glenn Gulak, on VLSI architectures for communication systems.
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1996: I worked six months in the Philips research laboratory of Paris
(LEP: Laboratoire d'Electronique de Philips, Limeil Brevannes, France)
on the developement of a real time MPEG-2 encoder circuit.
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1992-1995: I worked as a research engineer in the electronic departement
(ELEC) of ENST.
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1993-1995: Ph D thesis while working as a research engineer in ENST.
-
1990-1992: I worked as a professor in a telecommunication school of West
Africa (ESMT: Ecole Superieure Multinationale des Telecommunications) in
Dakar (Senegal).
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1986-1990: Undergraduate studies at ENST.

PhD students
Current PhD-Students :
- Cedric Marchand, "Architecture of LDPC decoders", PHd with NXP
- Aswhani Singh, "Flexible turbo/ldpc decoders", PHd with Guido Masera, Politecnico de Torino
- Arnaud Dion, "Flexible GALILEO/GPS receivers for satelite", PhD with SupAréo.
Former PhD-Students :
- Sébastien Trégaro (July 2009), "Détection et estimation de signaux radars", PHd with RUBISOFT
- Haisheng Liu (July 2009), "Contributions à la maîtrise de la consommation dans
des turbo-décodeurs", PHd with ENST-Bretagne, (PhD report (3.4 Mo))
- Jeremie Guillot (sept. 2008), "Optimization Techniques for
High Level Synthesis and pre-Compilation based on Taylor Expansion Diagrams",
joint project with prof. Ciesielski, (PhD report (4.7 Mo))
- Amor Nafkha, (march 2006), "Architecture MIMO", PHd, PALMYRE PROJECT (PhD report (2.4 Mo))
- Pierre Bomel ,
, "Automatic implementation of GALS", PHd PALMYRE PROJECT.
(PhD report (1.9 Mo))
- David Gnaedig, "Turbo-Codes à roulettes", PHd with Turbo-Concept
company.(PhD report (2.8 Mo))
- Frederic Guilloud, "Architecture générique de décodeur de codes LDPC" (PhD report (2.6 Mo))
- Olivier
Gay-Bellile , "Programmable architecture for channel decoding"
(abstract), (PhD report (1.2 Mo))
- Luis
Gonzalez, "VLSI architecture for combined source-channel coding"
(abstract), (PhD report (1.6 Mo))

Research and interest
My research area is in VLSI architectures and communications.
Current research area :
- Taylor Expansion Diagrams : (more information
in TED project).
- Low Density Parity Check code : (more information
in LDPC project).
- Non binary LDPC codes : (more information in DaVinci project (FP7)
Previous research area :
- Hardware correlator: (more information
in Hardware correlator project).
- Generic MIMO decoder: (more information
in Generic MIMO decoder project).
- (2001-2006) Slice Turbo Code : (more information
in Slice Turbo Code project).
- (2000-2002) White Gaussian Noise Generator for channel emulation (more information
in WGNG project).
- (1999-2001) Forward-Backward (or MAP, BJCR) project: this project deals on the construction of an WEB site
dedicated to VLSI for MAP algorithm. Some datas are presently available
(FORWARD-BACKWARD ARCHITECTURE).
- (1995-1999) Auger Project: During the 3 last years, I have also been involved in the design of the
telecommunication network of the international
AUGER
PROJECT (two 3000 km2 giant cosmic rays detector).

Industry collaborations
- demodulateur architecture and LDPC decoder architecture for DVB-S2 standard (2003-2005)
- ELINT systems(2005).
- Slice Turbo Code (since 2001).
- Specification and hardware realization of a familly of digital demodulators for
a radio application (1996-1999).
- Soft Reed-Solomon decoder (1998).
- Realisation of a real time "smart" Variable Length Coding for an MPEG-2
encoder (1997).
- First generation of a digital demodulator with a CLP ( FLEX10K50)
(1996).
- Realisation in standard cell (VHDL synthesis) of a real time DCT-IDCT for an MPEG-2 encoder (20 K gates, 27 MHz, precision compatible with the MPEG-2 standard) (1995).
- Work with the team that has defined the Array-Ol formalizen to describe array signal processing (1993 - 1994).
- Architecture study for an 30 MHz viterbi decoder for a 4 Dimentional TCM
modulation (1992).

Publications
Go here for the list of publications

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