Emmanuel Boutillon

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Professor at UBS (Universite de Bretagne Sud), Lorient, France, in the lab Lab-STICC (UMR 6285).




Work experience


PhD students

Current PhD-Students:
  1. Emmanuel Bodji, "Optimization of LDPC encoder/decoder with AI", PhD started 23 February 2023 (with Orange Labs, CIFRE)
  2. Abdallah Abdallah, "Simplified non-binary decoders", PhD started in 30 November 2023 (with Bertrand Legal, IRISA)

Former PhD-Students:

  1. Joseph Jabour, "High speed hardware implementation of non binary decoders", 01/11/2020-14/12/2023 (with LIU, Liban) , PhD Report (18 Mo), PhD defence (34 Mo)
  2. Camille Monière, "Hardware implementation of QCSP frames", (with Bertrand Le Gal, IPB/ENSEIRB-MATMECA), PhD Report (18 Mo), PhD defence (34 Mo)
  3. Titouan GENDRON, "Near ML turbo-decoders", 01/01/2019- 31/05/2022, (with prof. C. Abdel Nour, IMT-Atlantique), CIFRE with TurboConcept (PhD report available in 2027)
  4. Kassem SAIED, "Quasi Cyclic Short Packet (QCSP) transmission for Internet of Things", 01/09/2018-24/03/2022 (with Doc. A. Al Ghouwayel, LIU Beirut) , PhD Report (9.5 Mo), PhD defence (3.9 Mo)
  5. Vinh Hoang SON LE, (Mars 2021), "Design of Next-Generation Tbps Turbo Codes", (with prof. C. Douillard and prof. C. Abel Nour, IMT-Atlantique), PhD Report (3.15 Mo), PhD defence (2.5 Mo)
  6. Franklin COCHACHIN (May 2019), "Noised enhanced LDPC decoders", (PhD Report (4.9 Mo), PhD defence (2.8 Mo)
  7. Hassan HARB (December 2018), "Design Of Ultra-High Throughput Rate NB-LDPC Decoder", (PhD Report (2.2 Mo, in French), PhD defence (2.4 Mo)
  8. Mourad HAFIDHI (November 2017), "GPS on stochastic architecture", (PhD Report (2.2 Mo, in French), PhD defence (1.8 Mo, in French)
  9. Ahmed ABDMOULEH (September 2017), "Non-binary LDPC codes associated to high-order modulations", (PhD report (3.8 Mo), PhD defence (2.9 Mo)
  10. Oussama ABASSI (June 2014), "Etude des décodeurs LDPC non-binaires", (PhD report (2.5 Mo))
  11. Yangyang TANG (January 2013), "Computation on Unreliable Architecture" (PhD report (6.5 Mo)
  12. Arnaud DION (December 2012), "Récepteur de navigation reconfigurable pour applications spatiales", (PhD report (2.2 Mo)
  13. Cedric MARCHAND (January 2010), "Implementation of an LDPC decoder for the DVB-S2, -T2 and -C2 standards", PHd with NXP (PhD report (4.8 Mo)
  14. Aswhani SINGH (December 2009), "Flexible turbo/ldpc decoders", PHd with Guido Masera (Politecnico de Torino), (PhD report (4.4 Mo))
  15. Sébastien TREGARO (July 2009), "Détection et estimation de signaux radars", PhD with RUBISOFT
  16. Haisheng LIU (July 2009), "Contributions à la maîtrise de la consommation dans des turbo-décodeurs", PHd with ENST-Bretagne, (PhD report (3.4 Mo)
  17. Jeremie GUILLOT (September 2008), "Optimization Techniques for High Level Synthesis and pre-Compilation based on Taylor Expansion Diagrams", joint project with Prof. M. Ciesielski, PhD report (4.7 Mo)
  18. Amor NAFKHA, (March 2006), "Architecture MIMO", PhD, PALMYRE PROJECT (PhD report (2.4 Mo)
  19. David GNAEDIG (June 2005), "Turbo-Codes à roulettes", PhD with Turbo-Concept company.(PhD report (2.8 Mo))
  20. Pierre BOMEL (December 2004), , "Automatic implementation of GALS", PHd PALMYRE PROJECT. (PhD report (1.9 Mo))
  21. Frederic GUILLOUD (July 2004), "Architecture générique de décodeur de codes LDPC" (PhD report (2.6 Mo))
  22. Luis GONZALEZ (October 2000), "VLSI architecture for combined source-channel coding" (abstract), (PhD report (1.6 Mo))
  23. Olivier GAY-BELLILE (April 1999), "Programmable architecture for channel decoding" (abstract), (PhD report (1.2 Mo))


Research and interest

My research area is in VLSI architectures and communications.

Current research areas:

  1. AI-Aided FEC Decoding (a French ANR 2021-2024 grant) (more information in AI4Code project).
  2. Quasi Cyclic Short Pacquet (a French ANR 2019-2023 grant)(more information in QCSP project).
  3. Non binary LDPC codes: (more information in Current project)
  4. Low Density Parity Check code: (more information in LDPC project).

Previous research areas:

  1. Computation on unreliable architecture (more information in Unreliable Architecture project).
  2. Noise Against Noise Decoder (a French ANR 2015-2018 grant) (more information in NAND project).
  3. Trellis aggregation for high code rate turbo-code (more information in trellis aggregation).
  4. Turbo-Code architecture
  5. High speed time synchronization (more information in High speed Gardner algorithm).
  6. 8PSK demodulation: (more information in 8PSK project).
  7. Taylor Expansion Diagrams: (more information in TED project).
  8. Hardware correlator: (more information in Hardware correlator project).
  9. Generic MIMO decoder: (more information in Generic MIMO decoder project).
  10. (2001-2006) Slice Turbo Code: (more information in Slice Turbo Code project).
  11. (2000-2002) White Gaussian Noise Generator for channel emulation (more information in WGNG project).
  12. (1999-2001) Forward-Backward (or MAP, BJCR) project: this project deals on the construction of an WEB site dedicated to VLSI for MAP algorithm. Some datas are presently available (FORWARD-BACKWARD ARCHITECTURE).
  13. (1995-1999) Auger Project: During the 3 last years, I have also been involved in the design of the telecommunication network of the international AUGER PROJECT (two 3000 km2 giant cosmic rays detector).


Industry collaborations

  1. Hardware implementation of high speed DVB-S2 LDPC decoders
  2. Decoding architecture for Cortex code (2011-2014)
  3. Demodulateur architecture and LDPC decoder architecture for DVB-S2 standard (2009-2011, 2013-2014)
  4. ELINT systems(2005).
  5. Slice Turbo Code (since 2001).
  6. Specification and hardware realization of a family of digital demodulator for a radio application (1996-1999).
  7. Soft Reed-Solomon decoder (1998).
  8. Realisation of a real time "smart" Variable Length Coding for an MPEG-2 encoder (1997).
  9. First generation of a digital demodulator with a CLP (  FLEX10K50) (1996).
  10. Realisation in standard cell (VHDL synthesis) of a real time DCT-IDCT for an MPEG-2 encoder (20 K gates, 27 MHz, precision compatible with the MPEG-2 standard) (1995).
  11. Work with the team that has defined the Array-Ol formalizen to describe array signal processing (1993 - 1994).
  12. Architecture study for an 30 MHz viterbi decoder for a 4 Dimentional TCM modulation (1992).


Go here for the list of publications of 2012 and later

Go here for the list of publications before 2012


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