Taylor Expansion Diagrams

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Abstract

Recently a theory of a compact, canonical representation for arithmetic expressions, called (TED)has been proposed. This representation, based on a novel, non-binary decomposition principle, raises a level of design abstraction from bits to bit vectors and words, thus facilitating the verification of behavioral and RTL specifications of arithmetic designs. This paper presents the first practical results of using TED in the context of high-level design representation and verification. It discusses the use of TED for equivalence checking of behavioral and RTL designs and comments on its limitations. It also demonstrates the application of TEDs to verification of designs on algorithmic level and comments on their potential use in high level synthesis.

A joint project of research CNRS-NSF on this topic is currently developped (2002-2005) ( abstract of the project)

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More information

Presentation of HLDVT'02: slides.

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Related WEB sites

  1. The web site of professor Maciej Ciesielski.
  2. The web site of the TED package.
  3. The web site of Daniel Gomez.
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Related papers

  1. M. Ciesielski, D. Gomez-Prado, Q. Ren, J. Guillot, E. Boutillon, " Optimization of Data Flow Computations using Canonical TED Representation", Accepted to IEEE Transactions on Design & Test of Computers, april 2009.
  2. M. Ciesielski, J. Guillot, D. Gomez-Prado, Q. Ren, E. Boutillon, " High-level Transformations using Canonical Dataflow Representation", Accepted to IEEE Transactions on Computer-Aided Design of Integrated Circuits, TCAD, april 2009.
  3. D. Gomez-Prado, M. Ciesielski, J. Guillot, E. Boutillon, "Optimizing Data Flow Graphs to Minimize Hardware Implementation" Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09. ,DATE 2009, pp 117-122, Nice, April. 2009.
  4. Maciej Ciesielski, Serkan Askar, Emmanuel Boutillon, Jérémie Guillot, “Behavioral transformation for hardware synthesis and code optimization based on Taylor Expansion Diagrams”, United States Patent No. 7,472,359, Dec. 30, 2008. (deposal n°11/292,493, dec. 02, 2005).
  5. M. Ciesielski, S. Askar, D. Gomez-Prado, J. Guillot, E. Boutillon "Data-Flow Transformations Using Taylor Expansion Diagrams ", Design Automation and Test in Europe 2007, DATE'2007, Nice, April 2007
  6. J. Guillot, E. Boutillon, Q. Ren, M. Ciesielski, D. Gomez-Prado, S. Askar, "Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams", DATE'2006, Munich, 2006.
  7. D. Gomez-Prado, Q. Ren, S. Askar, M.Ciesielskin, E. Boutillon "Variable ordering for taylor expansion diagrams ", High-Level Design Validation and Test Workshop, HLDVT'04, pp 55-59, Nov. 2004
  8. Priyank Kalla, Maciej Ciesielski, Emmanuel Boutillon, Eric Martin, "High-level Design Verification using Taylor Expansion Diagrams: First Results", Accepted to the Seventh Annual IEEE International Workshop on High Level Design Validation and Test, HLDVT'02, Cannes, Oct. 2002.
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