Computation on unreliable architectures
One of the most critical challenges of the ITRS overall design technology (2010) is fault-tolerant computation. The increase in integration density and the requirement of low-energy consumption can only be sustained through low-powered components, with the drawback of a looser robustness against transient errors. In the near future, electronic gates to process information will be inherently unreliable.
An architectural level solution is to use error control codes in order to increase the reliability of operators and components.
In 2014, we start the 4-years RELIASIC project, funded by the Brittany Region and the Labex CominLab. The aim of the RELIASIC (Reliable Asic) project is to address this problem with a bottom-up approach, starting from an existing application (a GPS receiver) and adding some redundant mechanisms to allow the GPS receiver to be tolerant to transient errors due to low voltage supply.
The objective is to produce an ASIC with two versions of the application: a standard GPS receiver and a hardened GPS receiver (a simple L1 band GPS receiver). Our ambition is to decrease by a factor of 4 the energy of the hardened GPS receiver thanks to a very low power supply voltage while keeping an acceptable degradation of the quality of service provided by the device (Mean Time of First Fix, i.e. the mean time between a cold start and the first position given by the GPS receiver) and the variance of the error position estimation (few tens of meters).
During this project, we will develop knowledge at several levels: the effect of low voltage at transistor level, application of robust non-conventional arithmetic, the downstream impact of gate level errors on arithmetic and functional operation, refinement of high level specification (reliability and quality of service) to low level arithmetic and functional requirements. Measurement of the ASIC product will allow us to test the proposed methods on a real design case and provide very useful feedback.
More information on the reliasic project : RELIASIC Project
This 6 mn film (in French) presents the project for non-specialist:
PhD of Yangyang Tang (january 2013) : "Computation on Unreliable Architecture"
Abstract: This thesis addresses the issue of designing on unreliable circuit.
The main contributions are fourfold. Firstly a fast error-correction and
low cost redundancy fault-tolerant method is presented. Moreover,
we introduce judicious two-dimensional criteria to estimate the reli-
ability and the hardware efficiency of a circuit. A general-purpose
model offers low-redundancy error-resilience for contemporary logic
systems as well as future nanoeletronic architectures. At last, a
decoder against internal transient faults is designed in this work
Documents related to the PhD:
This research is done in collaboration with Prof. Chris Winstead (Utah State University)
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