Vianney Lapôtre

Associate professor at Université Bretagne Sud

ResearchCurrent research topics

  • Embedded processor security
  • Systems-on-Chip secutity
  • Hardware security

ResearchPrevious research topics

  • Reconfigurable and self-adaptive multiprocessor architectures

ResearchResearch Projects

  • Labex CominLabs SCRATCHS (2021-2024)
  • The goal of the SCRATCHS project is to co-design a RISC-V processor and a compiler toolchain to ensure by construction that a security sensitive code is immune to timing side-channel attacks while running at maximal speed

  • Labex CominLabs HardBlare (2015-2019)
  • The general context of the HardBlare project is to address hardware-assisted Dynamic Information Flow Control (DIFC) that generally consists in attaching marks to denote the type of information that are saved or generated within the system. These marks are then propagated when the system evolves and information flow control is performed in order to guarantee a safe execution and storage within the system.

  • ANR TSUNAMY (2013-2017)
  • The TSUNAMY project addresses the problem of secure handling of personal data and privacy in manycore architectures. The TSUNAMY project aims to propose a solution of trust building to execute many independent applications in parallel, safely and ensuring respect for the privacy of users.

  • PEPS SISC INS2I "HomCrypt" (2017)
  • Prototyping of a Hardware/Sofware design for homomophic encryption

Ph.D. GraduatesPh.D. Graduates

  • Maria Méndez Real (2014-2017)
    Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures
  • now Associate Professor at IETR-Polytech Nantes

  • Vincent Migliore (2014-2017)
    Hardware Cyber-Security and Design of Dedicated Components for Homomorphic Encryption Schemes
  • now Associate Professor at INSA Toulouse

  • Cyrielle Feron (2015-2018)
    PAnTHErS: Prototyping and Analysis Tool for Homomorphic Encryption Schemes
  • now at DGA-MI

  • Maria Mushtaq (2016-2019)
    Software-based detection and mitigation of microarchitectural attacks on Intel's x86 architecture
  • now Post-doc at LIRMM Montpellier

  • Ghita Harcha (2017-2021)
    Introducing shuffling into hardware architectures: a contribution to the security of AES cyphers in an IoT context
  • now at Tiempo Secure

Current Ph.D. studentsCurrent Ph.D. students

  • Nicolas Gaudin (2021-2024)
  • Design and avaluation of RISC-V processor robust against timing attacks

  • William Pensec (2021-2024)
  • RISC-V processor with DIFT robust against physical attacks

  • Noura Ait Manssour (2019-2022)
  • Secure processor against logical and physical attacks

Post-docsPost-docs

  • Arnab kumar Biswas (2018-2019)
  • multi-core/multiprocessor hardware-assisted DIFC system

M.Sc. GraduatesM.Sc. Graduates

  • Jérémy Bricq (2018)
  • Detection of cache-based side-channel attacks at the OS level

  • Samy Rida (2018)
  • Implementation of countermeasure techniques for cache-based timing side-channel attacks in multi- & many-core systems

  • Djelar Esperance Asngar (2015)
  • Analysis and comparison of GEM5 and OVPsim simulators

  • Thomas Toublanc (2015)
  • OS-integrated Multiprocessor platform implementation on FPGA

  • Charles Effiong (2014)
  • Performance Exploration of 3D NoCs with Resistive-Open TSVs

  • Robin Danilo (2012)
  • Branch prediction introduction in High Level Synthesis