Home My PhD thesis Délégation CNRS 2021-2022
From September 2021 to August 2022, I am in "délégation CNRS", meaning that I am acting as a full researcher during that period.
Relieving from the teaching activity allow to focus on my HdR and my scientific project.
The project focuses on the interaction between the processors and the memory, assuming a multi/many-core architecture with a centralized symmetric shared-memory architecture (SMP). The goal is to propose a new organisation for this interaction, called "notifying memory", which gives the capacity to the memory to initiate a transaction, avoiding the processor from constantly checking an updated value of a data, or using atomic memory operations.
The following figures show a logical view of the integration of the notifying memory concept, and an example for a 4-core SMP architecture with three levels of cache.
More to come.