Guy Gogniat Guy Gogniat, Professor

Lab-STICC Laboratory CNRS UMR 6285
Université Bretagne Sud
Centre de recherche Christiaan Huygens
CS 7030, 56321 LORIENT Cedex, FRANCE

phone: +33 (0)2 97 87 46 41


My research activity deals with embedded systems security.

Current research topics
      • Embedded systems security, cache-based side-channel attacks, Obfuscation techniques for HLS
Previous research topics
      • Adaptive computing, Rapid system prototyping on reconfigurable platforms, Software radio on reconfigurable platforms, Model based design methodologies, Communication architecture exploration for MPSoC systems, Verification of heterogeneous systems from an UML specification, Design space exploration for reconfigurable architectures, Performance estimation for FPGAs from a C specification, Hardware/software partitioning, Communication synthesis, Performance estimation for DSP

Current Ph.D. Students
      • Semih Ince, Securing cloud architectures based on the use of FPGA hardware accelerators (2021 - 2024)
      • Nicolas Gaudin, Development and evaluation of a RISC-V processor robust against side-channel attacks (2021 - 2024)
      • William Pensec, Protection of a RISC-V processor with DIFT against physical attacks (2021 - 2024)
      • Mohamed El Bouazzati, Low-power software-defined baseband RISC-V processor for flexibility and security (2020 - 2023)
      • Noura Ait Manssour, Hardware security for embedded processors against logical and physical attacks (2019-2022)
      • Asim Mukhtar, Enhanced cache architecture to protect embedded system security against cache-based side-channel attacks (2016 - 2022)
  • Arnab kumar Biswas, multi-core/multiprocessor hardware-assisted DIFC system (2018 - 2019)
  • Martha Johanna Sepulveda, Security implementation in communication structure for 3D SoC protection (2012 - 2013)
  • Leandro Fiorin, Fault tolerance in Network on Chip (2013)
  • Eduardo Wanderley, A Code Compression Method With Confidentiality and Integrity Checking (2006 - 2007)
Ph.D. Graduates
      • Hannah Badier Boenning, Obfuscation techniques for HLS in SaaS mode (2017 - 2021)
      • Maria Mushtaq, Software-based Detection and Mitigation of Microarchitectural Attacks on Intel’s x86 Architecture (2016 - 2019)
        Associate Professor at Telecom Paris
      • Muhammad Abdul Wahab, Hardware coprocessor for Dynamic Information Flow Tracking in MPSoC systems (2015 - 2018)
        R&D Engineer at Ultraflux
      • Maria Mendez, Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures (2014 - 2017)
        now Associate Professor at IETR-Polytech Nantes
      • Vincent Migliore, Hardware Cyber-Security and Design of Dedicated Components for Homomorphic Encryption Schemes (2014-2017)
        now Associate Professor at INSA Toulouse
      • Safae Dahmani, Cooperative caching for CMP (2012-2015)
        now Distributed Systems Performance Engineer at Hadean, United Kingdom
      • Simon Fau, Cryptocomputing systems, compilation and runtime (2011-2016)
        now Consultant in Cybersecurity at ADENTIS, France
      • Vianney Lapotre, Management of reconfigurable multi-standards ASIPs-based receiver (2010 - 2013)
        now Associate Professor at ENSIBS/Lab-STICC, Lorient, France
      • Pascal Cotret, Distributed security for communications and memories in a multiprocessor architecture (2009 - 2012)
        now Associate Professor at ENSTA Bretagne, Brest, France
      • Sébastien Guillet, Modeling and Formal Control of Partial Dynamic Reconfiguration (2009 - 2012)
        now Lecturer at
        ENSIBS/Lab-STICC, Lorient, France 
      • Martha Johanna Sepúlveda Flórez, Proposition of NoC architectures and design tool for quality of service and security challenges (2008 - 2011)
        now Senior Scientist Secure Communications at Airbus Defence and Space - Intelligence, Germany
      • Jérémie Crenne, Embedded system security (2008 - 2011)
        now Associate Professor at ENSEIRB-MATMECA/IMS, Bordeaux,
      • Michael Grand, Cryptoprocessor for Software Defined Radio (2008 - 2011)
        now R&D Manager, Deputy Technical Manager and Process Improvement Manager at SERMA Safety & Security
        , France
      • Linfeng Ye, Self-adaptative Multi-processor System-on-Chip : Architecture, Methodology and Decision (2007 - 2010)
        now Assistant Professor at Guangdong University of Technology, Guangzhou, P.R China
      • Jorgiano vidal, Dynamic and partial reconfigurable embedded systems design with UML (2007 - 2010) 
        now Associate Professor at Federal Tecnological Education Center of Rio Grande do Norte, Brazil 
      • Rasmus Abildgren, Implementation Effort and Parallelism - Metrics for Guiding Hardware/Software Partitioning in Embedded System Design (2006 - 2010)
        now Bluetooth Standards Architect at Bose Corporation, Denmark 
      • Gaël Abgrall, Software Defined Radio and dynamic reconfiguration (2007 - thesis interruption in 2010)
        now engineer at DC-DIRISI, Paris, France
      • Yassine Aoudni, Rapid system prototyping of reconfigurable platforms (2003 - 2010)
        now Assistant Professor at ENIS, Sfax, Tunisia
      • Romain Vaslin, Hardware Core for Off-chip Memory Security Management in Embedded Systems (2005 - 2008)
        now engineer at Thales Communications, Cholet, France
      • Issam Maalej, Communication architecture exploration for MPSoC systems (2002 - 2006)
        now R&D engineer at SYLEPS Group, Lorient, France
      • Samuel Rouxel, Modeling and characterization of heterogeneous SoC platform: Application to SDR (2002 - 2006)
        now R&D engineer at CRESITT Industrie, Orléans, France
      • Lilian Bossuet, Design space exploration of reconfigurable architectures (2001 - 2004)
        now Professor at Université Jean Monnet Saint-Etienne, Telecom Saint-Etienne, France
      • Sébastien Bilavarn, Architectural exploration from a C specification: FPGAs case study (1999 - 2002)
        now Associate Professor at University of Nice-Sophia Antipolis, France

M.Sc. Graduates
      • Jérémy Bricq, Detection of cache-based side-channel attacks at the OS level - 2018
      • Samy Rida, Implementation of countermeasure techniques for cache-based timing side-channel attacks in multi- & many-core systems - 2018
      • Djelar Esperance Asngar, Analysis and comparison of GEM5 and OVPsim simulators - 2015
      • Thomas Toublanc, OS-integrated Multiprocessor platform implementation on FPGA - 2015
      • Satyajit Das, A Diffie Hellman reconfigurable security architecture in NOC-based MPSoC architectures - 2014
      • Cédric Maignan, Network Contention-aware Method to Evaluate Data Consistency Protocols within a Compilation Toolchain - 2014
      • Hamza Chaker, Cycle-based Model to Evaluate Consistency Protocols within a Multi-protocol Compilation Toolchain - 2014
      • Soukaina Benamar, Design of Multiprocessor Systems on Chip - 2011
      • Said Louizi, Firewall for communication protection within embedded systems - 2011
      • Cedric Seguin, Reconfigurable architecture and security: how to handle remote partial reconfiguration securely - 2010
      • Naoufel Belfathi, Multithreading on XilKernel for multiprocessor systems - 2010
      • Abdessalam Chafik, Communication protection within embedded systems - 2010
      • Jérémie crenne, Remote partial reconfiguration through network protocol - 2008
      • Yaset Oliva, Bitstream server for reconfigurable system on chip - 2008
      • Zui Tao, Asymetric Encryption Algorithm: Implemntation on Nios-based systems - 2007
      • Sylvain Ducloyer, Hardware architecture for haching functions: Application to MD5/SHA-1/SHA-2 - 2007
      • Arnaud Dumérat, Fault detection and fault tolerant ECC algorithm - 2006,
      • Jérémie Guillot, Cryptography and self dynamic reconfiguration on an FPGA platform – 2004
      • Jean Philippe Delahaye, Software radio and dynamic reconfiguration on a DSP/FPGA platform – 2003
      • Erwan Piriou, Reconfigurable technologies and programmable technologies: a comparison – 2003
      • Samuel Rouxel, Routing cost on FPGA architectures – 2002
      • Issam Maalej, Interface synthesis for SoC – 2002
      • Lilian Bossuet, Modeling of reconfigurable architectures: toward a generic approach – 2001
      • Said Chaboun, Implementation of audio coding onto heterogeneous architectures – 1999


Several fundings support my research activity: CNRS, RNRTRNTL, DGA, CMCU, Brittany State, ANR...
Below is a summary of most relevant projects: 

  • SCRATCHS (2021-2024): Side-Channel Resistant Applications Through Co-designed Hardware/Software is a collaboration between researchers in the fields of formal methods (Celtique, Inria Rennes), security (Cidre, CentraleSupélec Rennes) and hardware design (Lab-STICC). Our goal is to co-design a RISC-V processor and a compiler toolchain to ensure by construction that a security sensitive code is immune to timing side-channel attacks while running at maximal speed. Our claim is that a co-design is essential to get end-to-end security: cooperation between the compiler and hardware is necessary to avoid time leaks due to the micro-architecture with minimal overhead.
  • HardBlare (2015-2019): The general context of the HardBlare project is to address hardware-assisted Dynamic Information Flow Control (DIFC) that generally consists in attaching marks to denote the type of information that are saved or generated within the system. These marks are then propagated when the system evolves and information flow control is performed in order to guarantee a safe execution and storage within the system.
  • TSUNAMY project (2013-2017): The TSUNAMY project addresses the problem of secure handling of personal data and privacy in manycore architectures. The TSUNAMY project aims to propose a solution of trust building to execute many independent applications in parallel, safely and ensuring respect for the privacy of users. For this, several contributions are proposed: 1) development of a processing cluster to run both algorithms for processing information and cryptographic algorithms (with a strong level of coupling for performance reasons but while ensuring no leakage of information), 2) development of a manycore architecture integrating heterogeneous clusters for secure cryptographic, 3) development of mechanisms for logical isolation (in software) and physical (hardware level) to ensure execution of partitioned applications, 4) joint development of software layers (driver, API ...) and hardware to provide a chain of trust and 5) development of strategies for dynamically distributing applications on a manycore architecture . All of these contributions will be validated through simulation modeling using SystemC CABA. SoCLib environment and the TSAR architecture and the ALMOS operating system will be used to validate the project. The TSUNAMY project aims to provide the scientific community of academic and industrial with models of architectures and software libraries to efficiently and securely deploy applications on
    manycore architectures.
  • FAMOUS project (2010-2013): This project aims at introducing a complete methodology that takes the reconfigurability of the hardware as an essential design concept and proposes the necessary mechanisms to fully exploit those capabilities at runtime. The project covers research in system models, compile time and run time methods, and analysis and verification techniques. These tools will provide high-quality designs with improved designer productivity, while guaranteeing consistency with the initial requirements for adaptability and the final implementation. 
  • SecReSoC project (2010-2013): The goals of the SecReSoC project are to increase the security level of reconfigurable technologies (FPGAs) at the logic, architectural and system levels. FPGA technology has been selected as it becomes widespread in many application domains and corresponds to a strong vector to prototype and to evaluate the security level of cryptographic architectures. A generic MPSoC architecture enabling the integration into an FPGA of an application requiring a multilevel security data protection will be designed, implemented and tested. This multiprocessor architecture will include an optimized cryptoprocessor for implementation of cryptographic protocols and encryption modes; some standard processors for multitasking OS implementation; internal data memories and an interface to external data memories; input/output units and an internal communication structure integrating and enabling several security levels. Tools for secured device reconfiguration will be proposed also. System security will be evaluated and side-channel attacks
    will be considered during system design and evaluation. The final aim of the project will be the design of a prototype to evaluate the cost and the efficiency of the proposed techniques. 
  • MOPCOM projet (2006 - 2009): The MOPCOM project is focused on model engineering using MDA approaches to develop SoC/SoPC. The project aims to provide a formalized design process (design methodology) and the associated tools in order to target: The design at different levels of abstraction, from system TLM level down to architecture RTL level. The design of reconfigurable systems that may be reconfigured at run time. A MDA/MDE prototype tool will be developed during the project that will perform code generation (SystemC and VHDL) from a specification description using UML. This prototype will rely on adapted profiles for real time embedded system from the system description down to the architecture description. 
  • AEther Project (2006 - 2009): European citizens are now living in a world of "pervasive computing", where virtually every object has a processing power. Undoubtedly, computing devices are more ubiquitous and interconnected than ever, fulfilling the most varied tasks with little human intervention. The size of these "pervasive computing" networks is significantly increasing, as well as the variety of the computing devices, both at chip (multicore and reconfigurable architectures) and system level (distributed processing). As their scope of application broadens, processing resources require greater flexibility and scalability to meet the various needs of users. AETHER's main objectives are to study, evaluate and propose novel computing architectures  responding to the most demanding embedded applications in the next 10+ years. In particular, the AETHER project aims to tackle the issues related to the performance and technological scalability, increased complexity and programmability of future embedded computing architectures by introducing self-adaptive technologies in computing resources.
  • ICTeR Project (2006 - 2009): Digital integrated systems have supplanted the paper as the media through which the information is transmitted, thus a great interest for cryptology has emerged at all levels of the integrated circuit design flow. The physical implementation has indeed become the Achille’s Heel of secured platforms while side channel attacks such as the Differential Power Analysis have become common and popular. It is now well known and accepted that side channel attacks are the most efficient attacks since they require only little knowledge and material to be successfully applied. In this context, this project aims at analysing the potential benefits in terms of security of physical reconfigurable platforms and devices. More precisely, this projects aims at (a) defining ad-hoc integration techniques of cryptography primitives on such platforms and (b) and at defining what is the ideal reconfigurable platform allowing the best possible integration of cryptography primitives.
  • SANES Project (2004 - 2005): Embedded System Security is becoming a major issue to enable the vision of ubiquitous computing. Numerous challenges need to be addressed to promote security within future embedded systems. Our research aims at defining new solutions to leverage embedded systems security by taking benefit of reconfigurable architectures and on-chip hardware monitoring. We also propose new solutions to improve security within future NoC.
  • A3S Project (2003 - 2005): This project defines a new methodology for software radio systems validation, entirely based on UML. Right at the modeling step it will be possible to perform non-functional coherence verification of software radio architecture specifications and application requirements with UML based models. The interest of such an approach is to give the designers the opportunity to investigate, before beginning any development step, the array of potential solutions and enabling selection of some by verification of the coherency. This approach enables design cost saving by drastic reduction of time and minimization of the number of prototypes.
  • EPICURE Project (2001 - 2003): This project defines a new design methodology able to bridge the gap between an abstract specification and an heterogeneous reconfigurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are: i) a generic HW/SW interface model, ii) a specification methodology that handles the control, and includes efficient verification and HW/SW synthesis capabilities, iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The EPICURE framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can significantly improve the designer productivity, especially in the context of reconfigurable architectures.


I teach within the University of Bretagne-Sud

I am involved in the following courses:
  • Analog and digital design
  • Control systems
  • C language
  • Computer science

Publications (dblp)


Climbing in brittany, it is a great place (in french)