My research activity deals with adaptive computing, model based design methodologies, reconfigurable architectures, rapid system prototyping, embedded system security and hardware/software codesign.

Current research topics

• Adaptive computing
• Rapid system prototyping on reconfigurable platforms
• Software radio on reconfigurable platforms
• Embedded systems security
• Model based design methodologies
  

Previous research topics

• Communication architecture exploration for MPSoC systems
• Verification of heterogeneous systems from an UML specification
• Design space exploration for reconfigurable architectures
• Performance estimation for FPGAs from a C specification
• Hardware/software partitioning
• Communication synthesis
• Performance estimation for DSP

Current Ph.D. Students

• Milad El Khodary, Operating Environment for Self Adaptive Networked Entities (SANES) (2006 - 2012)
• Pascal Cotret, Distributed security for communications and memories in a multiprocessor architecture (2009 - 2012)
• Sébastien Guillet, Modeling and Formal Control of Partial Dynamic Reconfiguration (2009 - 2012)
• Vianney Lapotre, Management of reconfigurable multi-standards ASIPs-based receiver (2010 - 2013)
• Simon Fau, Crypto-engines for homomorphic cryptography (2011-2014)
  

Ph.D. Graduates

• Jérémie Crenne, Embedded system security (2008 - 2011)
  now Post-Doc at LIRMM, Montpellier, France
• Michael Grand, Cryptoprocessor for Software Defined Radio (2008 - 2011)
  now Assistant Professor at University of Science and Technologies of Bordeaux, France
• Linfeng Ye, Self-adaptative Multi-processor System-on-Chip : Architecture, Methodology and Decision (2007 - 2010)
  now Assistant Professor at Guangdong University of Technology, Guangzhou, P.R China
• Jorgiano vidal, Dynamic and partial reconfigurable embedded systems design with UML (2007 - 2010) 
  now Associate Professor at Federal Tecnological Education Center of Rio Grande do Norte, Brazil 
• Rasmus Abildgren, Implementation Effort and Parallelism - Metrics for Guiding Hardware/Software Partitioning in Embedded System Design (2006 - 2010)
  now a Software Engineer at CSR, Alborg, Denmark 
• Gaël Abgrall, Software Defined Radio and dynamic reconfiguration (2007 - thesis interruption in 2010)
  now engineer at DC-DIRISI, Paris, France
• Yassine Aoudni, Rapid system prototyping of reconfigurable platforms (2003 - 2010)
  now Teaching Assistant at ENIS, Sfax, Tunisia
• Romain Vaslin, Hardware Core for Off-chip Memory Security Management in Embedded Systems (2005 - 2008)
  now an engineer at Thales Communications, Cholet, France
• Issam Maalej, Communication architecture exploration for MPSoC systems (2002 - 2006)
  now an R&D engineer at Sydel, Lorient, France
• Samuel Rouxel, Modeling and characterization of heterogeneous SoC platform: Application to SDR (2002 - 2006),
  now an R&D engineer at CRESITT Industrie, Orléans, France
• Lilian Bossuet, Design space exploration of reconfigurable architectures (2001 - 2004), 
  now an Associate Professor at University of Saint-Etienne, France
  
• Sébastien Bilavarn, Architectural exploration from a C specification: FPGAs case study (1999 - 2002),
  now an Associate Professor at University of Nice-Sophia Antipolis, France
  

M.Sc. Graduates

• Soukaina Benamar, Design of Multiprocessor Systems on Chip - 2011
• Said Louizi, Firewall for communication protection within embedded systems - 2011
• Cedric Seguin, Reconfigurable architecture and security: how to handle remote partial reconfiguration securely - 2010
  now a PhD student at Lab-STICC, Lorient, France
• Naoufel Belfathi, Multithreading on XilKernel for multiprocessor systems - 2010
• Abdessalam Chafik, Communication protection within embedded systems - 2010
• Jérémie crenne, Remote partial reconfiguration through network protocol - 2008,
  now a PhD student at Lab-STICC, Lorient, France
• Yaset Oliva, Bitstream server for reconfigurable system on chip - 2008,
  now a PhD student at IETR, Rennes, France
• Zui Tao, Asymetric Encryption Algorithm: Implemntation on Nios-based systems - 2007,
  now a Master student at Université de Bretagne Sud, Lorient, France
• Sylvain Ducloyer, Hardware architecture for haching functions: Application to MD5/SHA-1/SHA-2 - 2007
  now an engineer at Lab-STICC, Lorient, France
• Arnaud Dumérat, Fault detection and fault tolerant ECC algorithm - 2006,
  
• Jérémie Guillot, Cryptography and self dynamic reconfiguration on an FPGA platform – 2004,
  now a Post Doc at Lab-STICC, Lorient, France
• Jean Philippe Delahaye, Software radio and dynamic reconfiguration on a DSP/FPGA platform – 2003,
  now an R&D engineer at CELAR, Rennes, France
• Erwan Piriou, Reconfigurable technologies and programmable technologies: a comparison – 2003,
  now a R&D engineer at CEA, Orsay, France
• Samuel Rouxel, Routing cost on FPGA architectures – 2002,
  now an R&D engineer at CRESITT Industrie, Orléans, France
• Issam Maalej, Interface synthesis for SoC – 2002,
  now an R&D engineer at Sydel, Lorient, France
• Lilian Bossuet, Modeling of reconfigurable architectures: toward a generic approach – 2001,
  now an Associate Professor at University of Science and Technologies of Bordeaux
• Said Chaboun, Implementation of audio coding onto heterogeneous architectures – 1999

• FAMOUS project (2010-2012): This project aims at introducing a complete methodology that takes the reconfigurability of the hardware as an essential design concept and proposes the necessary mechanisms to fully exploit those capabilities at runtime. The project covers research in system models, compile time and run time methods, and analysis and verification techniques. These tools will provide high-quality designs with improved designer productivity, while guaranteeing consistency with the initial requirements for adaptability and the final implementation. 
• SecReSoC project (2010-2012): The goals of the SecReSoC project are to increase the security level of reconfigurable technologies (FPGAs) at the logic, architectural and system levels. FPGA technology has been selected as it becomes widespread in many application domains and corresponds to a strong vector to prototype and to evaluate the security level of cryptographic architectures. A generic MPSoC architecture enabling the integration into an FPGA of an application requiring a multilevel security data protection will be designed, implemented and tested. This multiprocessor architecture will include an optimized cryptoprocessor for implementation of cryptographic protocols and encryption modes; some standard processors for multitasking OS implementation; internal data memories and an interface to external data memories; input/output units and an internal communication structure integrating and enabling several security levels. Tools for secured device reconfiguration will be proposed also. System security will be evaluated and side-channel attacks
  will be considered during system design and evaluation. The final aim of the project will be the design of a prototype to evaluate the cost and the efficiency of the proposed techniques. 
• MOPCOM projet (2006 - 2009): The MOPCOM project is focused on model engineering using MDA approaches to develop SoC/SoPC. The project aims to provide a formalized design process (design methodology) and the associated tools in order to target: The design at different levels of abstraction, from system TLM level down to architecture RTL level. The design of reconfigurable systems that may be reconfigured at run time. A MDA/MDE prototype tool will be developed during the project that will perform code generation (SystemC and VHDL) from a specification description using UML. This prototype will rely on adapted profiles for real time embedded system from the system description down to the architecture description. 
• AEther Project (2006 - 2009): European citizens are now living in a world of "pervasive computing", where virtually every object has a processing power. Undoubtedly, computing devices are more ubiquitous and interconnected than ever, fulfilling the most varied tasks with little human intervention. The size of these "pervasive computing" networks is significantly increasing, as well as the variety of the computing devices, both at chip (multicore and reconfigurable architectures) and system level (distributed processing). As their scope of application broadens, processing resources require greater flexibility and scalability to meet the various needs of users. AETHER's main objectives are to study, evaluate and propose novel computing architectures  responding to the most demanding embedded applications in the next 10+ years. In particular, the AETHER project aims to tackle the issues related to the performance and technological scalability, increased complexity and programmability of future embedded computing architectures by introducing self-adaptive technologies in computing resources.
• ICTeR Project (2006 - 2009): Digital integrated systems have supplanted the paper as the media through which the information is transmitted, thus a great interest for cryptology has emerged at all levels of the integrated circuit design flow. The physical implementation has indeed become the Achille’s Heel of secured platforms while side channel attacks such as the Differential Power Analysis have become common and popular. It is now well known and accepted that side channel attacks are the most efficient attacks since they require only little knowledge and material to be successfully applied. In this context, this project aims at analysing the potential benefits in terms of security of physical reconfigurable platforms and devices. More precisely, this projects aims at (a) defining ad-hoc integration techniques of cryptography primitives on such platforms and (b) and at defining what is the ideal reconfigurable platform allowing the best possible integration of cryptography primitives.
• SANES Project (2004 - 2005): Embedded System Security is becoming a major issue to enable the vision of ubiquitous computing. Numerous challenges need to be addressed to promote security within future embedded systems. Our research aims at defining new solutions to leverage embedded systems security by taking benefit of reconfigurable architectures and on-chip hardware monitoring. We also propose new solutions to improve security within future NoC.
• PROSYR Project (2003 - 2005): This project defines a methodology for rapid prototyping of real time embedded systems. Our approach deals with design space exploration from system level to physical implementation. The design flow is based on several steps that enable the designer to progressively refine his implementation. Metrics at the system level define the orientation of the application (control, data, memory). Clustering techniques promote the definition of MPSoC systems. Hardware and software estimation techniques are also evaluated in order to provide performance evaluation from a system level specification. RTOS are taken into account to provide a fine scheduling of the application onto the heterogeneous platform.
• A3S Project (2003 - 2005): This project defines a new methodology for software radio systems validation, entirely based on UML. Right at the modeling step it will be possible to perform non-functional coherence verification of software radio architecture specifications and application requirements with UML based models. The interest of such an approach is to give the designers the opportunity to investigate, before beginning any development step, the array of potential solutions and enabling selection of some by verification of the coherency. This approach enables design cost saving by drastic reduction of time and minimization of the number of prototypes.
• EPICURE Project (2001 - 2003): This project defines a new design methodology able to bridge the gap between an abstract specification and an heterogeneous reconfigurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are: i) a generic HW/SW interface model, ii) a specification methodology that handles the control, and includes efficient verification and HW/SW synthesis capabilities, iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The EPICURE framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can significantly improve the designer productivity, especially in the context of reconfigurable architectures.
• MACGTT Project (2000 - 2002): This project proposes an original design flow that performs a progressive design space reduction. In order to fully take benefit of the optimization potential from the applications and the architectures, our flow realizes a large parallelism exploration at the algorithmic level before the definition of the target architecture. Then, based on the highlighted solutions during the exploration step, an hardware/software partitionning phase enables the refinement of the solutions to converge to the characterized final architecture.

I teach within the University of Bretagne-Sud

I am involved in the following courses:

Climbing in brittany, it is a great place (in french)