Arnaud TISSERAND

CNRS "Directeur de Recherche" / Senior Researcher, ARCAD research group, Lab-STICC Laboratory

MÉDIATION SCIENTIFIQUE (Français)

présentations et ateliers pour le grand public, fête de la science, ...

 

News and events (Archives)

Seminar on Security of Embedded Electronic Systems (archives 2014-2018)

Conferences 2022
May: PHISICS (16-17, Gardanne)
Sep.: ARITH (Virtual)

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Research

Topics

Computer arithmetic: number systems, algorithms for efficient operations, arithmetic operators/accelerators, secure operators, low-power implementations

Hardware and software implementations of cryptographic systems: asymmetric cryptography in hardware and embedded software, (H)ECC operators and crypto-processor, protections/countermeasures against side channel attacks, arithmetic support for crypto and embedded systems, finite-field arithmetic, software protections against physical attacks

Hardware architectures and accelerators: application specific processors on FPGAs, ASICs, GPUs and embedded multicores

VLSI design and CAD tools: ASIC and FPGA circuits, asynchronous circuits, low power consumption, circuit generation tools

Applications: embedded systems, digital security, cyber-security/defense, scientific computing, digital signal processing, image processing, digital control.

Current/Recent Professional Activities

2021+: Associate Editor of the Transactions on Emerging Topics on Computing

2017-now: Organizer of the Hardware & Embedded Software Security Working Group at Lab-STICC

2014-now: Organizer of the Seminar on Security of Embedded Electronic Systems

2020: General co-Chair of the 8th International Workshop on the Arithmetic of Finite Fields (WAIFI 2020)

2020: Program Committee co-Chair of the 27th Symposium on Computer Arithmetic (ARITH 2020)

2019: President of the organisation committee of the french École thématique ARCHI

2018-2021: Head of ARCAD research group in Lab-STICC

2018: General Chair of CryptArchi 2018 (June, 17-20, Lorient, France)

2017-2021: Membre du comité de thèses de l'école doctorale MATHSTIC

Current/Recent Projets and Collaborations

2014-2017: Reliasic project with IRISA, Lab-STICC, IETR (funded by Labex CominLabs and Brittany Region)

2014-2017: H-A-H (Hardware and Arithmetic for Hyperelliptic Curves Cryptography) project with IRISA, Lab-STICC, IRMAR (funded by Labex CominLabs, Labex Lebesgue and Brittany Region)

2012-2016: PAVOIS project with IRISA, LIRMM (funded by ANR Programme "Blanc" 2012)

2011-2016: ARDYT (Reliable and Reconfigurable Dynamic Architecture) project with IRISA, Lab-STICC, LCIM and Atmel (funded by ANR Programme "Ingénerie Numérique et Sécurité" 2011)

Recent Presentations

Invited presentation at GDR Sécurité et SoC2 (Nov. 2021) on "Experience Feedback on HLS Implementation of LWE PQC on FPGA" (Paris, France). (slides PDF)

Invited presentation at ENS Paris-Saclay (Sept. 2021) on "Introduction to Efficient and Secure Arithmetic Circuits" (Visio-conference, Paris, France). (slides PDF)

Invited presentation at SILM Workshop on Software/Hardware Security (Nov. 2019) on "Hardware-Software Co-Design for Security: ECC Processor Example" (Rennes, France).

Invited presentation at SPEC CEA Saclay (Nov. 2019) on "Introduction to Computer Arithmetic for Efficient Hardware Implementations" (Paris, France).

Invited presentation at 30 ans du LIP (Nov. 2018) on "Protection des circuits arithmétiques contre les attaques physiques" (Lyon, France).

Invited presentation at La sécurité de l,objet connecté (Oct. 2018) on "Introduction to Physical Attacks" (Nantes, France).

Invited keynote at CRiSIS 2017 on Hardware Support for Physical Security (PDF slides)

Invited presentation at CEA NanoInnov (July 2017) on Arithmetic Tradeoffs on Performance/Cost/Security for Hardware Asymmetric Cryptography

Invited presentation at Colloque National du GDR SOC2 (June 2017) on Embedding Crypto in SoCs: Threats and Protections

Invited presentation at ECC (September 2015) on Hardware Accelerators for ECC and HECC

Links

Symposia on Computer Arithmetic ARITH (main link), editions:

Seminars on Seminar on Security of Embedded Electronic Systems

Links to colleagues and groups

SAGE: a free open-source mathematics software system (book in french)

GDR du CNRS : IM - Arith - C2 / SoC-SiP / ISIS / Sécurité

ACM: digital library, conferences, publications, special interest groups [ SIGACT, SIGARCH, SIGBED, SIGDA, SIGMICRO, SIGSAC ]

IACR

IEEE: digital library, societies : [ CAS, CS, ITS, SSCS ]

Création du Groupe Thématique SMAI-MAIRCI

Société informatique de France (SIF)

Bulletin de la société informatique de France

Agence pour les mathématiques en interaction avec l'entreprise et la société (AMIES)

Workshops CryptArchi

Interstices (site de culture scientifique autour de l'informatique)

Images des mathématiques

Chercheur français, une espèce en voie de disparition ? / French researcher, a critically endangered species?

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Publications (Complete list / co-authors)

Some recent publications

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Students (Complete list)

Current PhD students

Johann Milon, 2021-in progress (50% working time on the PhD), Ministère des Armées and Lab-STICC

Morgane Vollmer, 2020-in progress, UBO Lab-STICC (grant DGA-PEC, co-advisors: K. Bigou and L. Nana)

Fabrice Lozachmeur, 2020-in progress, Thales and Lab-STICC

Noura Ait Manssour, 2019-in progress, CNRS Lab-STICC (grant ARED-PEC, co-advisors: G. Gogniat and V. Lapôtre)

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Software/Hardware

LWE crypto in HLS on FPGA
Implementation of round-2 KEM candidates based on lattices: LWE, RLWE, MLWE, multiple levels of parallelism, various choices of the PRNG, CPA and CCA secure solutions.
Hyper-threaded modular multipliers (HTMMs) generator
Fast, small and efficient GF(P) multipliers for elliptic curve cryptography (ECC) and hyper-elliptic curve cryptography (HECC) [development in the HAH project]
Seedgen
Seeds circuit generator (1/x and 1/sqrt(x))
MEPLib
Machine Efficient Polynomial Library
Divgen
A divider unit generator
FLIP
Floating-Point Library for Integer Processors

Links on softwares: AFUL

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Teaching / Enseignement (Archives)

Séminaires d'introduction aux TRNG et à la cryptanalyse.

Organisation et cours d'écoles thématiques

Co-organisation et cours à l'école thématique ARCHI19 : Architectures des systèmes matériels enfouis et méthodes de conception associées (20-24 mai, 2019, Lorient)

Co-organisation et cours à l'école thématique ARCHI17 : Architectures des systèmes matériels enfouis et méthodes de conception associées (6-10 mars, 2017, Nancy)

Co-organisation et cours à l'école thématique ARCHI15 : Architectures des systèmes matériels enfouis et méthodes de conception associées (8-12 juin, 2015, Lille)     [ slides PDF: Processor Extensions for Security ]

Cours à l'école thématique ECOFAC2014 : Conception faible consommation pour les systèmes embarqués temps réel (19-23 mai 2014, Lorient)

Co-organisation et cours à l'école thématique ARCHI13 : Architectures des systèmes matériels enfouis et méthodes de conception associées (25-29 mars, 2013, Col-de-Porte)     [ slides PDF: Introduction to FPGA Circuits ]

Co-organisation et cours à l'école thématique ECOFAC2012 : Conception faible consommation pour les systèmes embarqués temps réel (21-25 mai 2012, La Colle-sur-Loup)

Co-organisation et cours à l'école thématique ARCHI11 : Architectures des systèmes matériels enfouis et méthodes de conception associées (2 - 6 mai, 2011, Mont-Louis)

Co-organisation et cours à l'école thématique ECOFAC2010 : Conception faible consommation pour les systèmes embarqués temps réel (29 mars - 2 avril, 2010, Plestin les Grèves, Côtes d'Armor)

Co-organisation et cours à l'école thématique ARCHI09 : Architectures des systèmes matériels enfouis et méthodes de conception associées (30 mars - 3 avril, 2009, Pleumeur-Bodou)

Co-organisation et cours à l'école thématique ARCHI07 : Architectures des systèmes matériels enfouis et méthodes de conception associées (19-23 mars, 2007, Boussens)

Organisation et cours à l'école thématique ARCHI05 : Architectures des systèmes matériels enfouis et méthodes de conception associées (21-25 mars, 2005, Autrans)

Co-organisation et cours à l'école thématique ARCHI03 : Architectures des systèmes matériels enfouis et méthodes de conception associées (31 mars - 4 avril, 2003, Roscoff)


Site web permanent sur les écoles thématiques ARCHI

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Contact

Arnaud Tisserand

E-mail :
arnaud.tisserand@cnrs.fr
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Tel :
(+33) (0)2 97 87 46 49
Address/Adresse :
CNRS, Lab-STICC, Centre de recherche UBS Huygens, Rue St Maudé, CS 7030, 56321 Lorient cedex, France

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Vitae

Short biography

Arnaud Tisserand, PHD 1997 and HDR 2010, is senior researcher ("directeur de recherche" in french) at CNRS (French National Center for Scientific Research) in computer science in Lab-STICC laboratory and the Architecture research group. His research interests include computer arithmetic, computer architecture, digital security, VLSI and FPGA design, design automation, low-power design and applications in applied cryptography, scientific computing, digital signal processing. He taught computer arithmetic, computer architecture, VLSI design, applied cryptography and Python programming.