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News and events (Archives)

Seminars on Security of Embedded Electronic Systems

Conferences 2018

June: CryptArchi (Lorient, France), ARITH (Amherst, MA, USA)

July: COMPAS (Toulouse, France)

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Research

Topics

Computer arithmetic: operations, elementary functions, number systems, secure operators, reliable arithmetic...

Applied cryptography: asymmetric cryptography in hardware or embedded software, (H)ECC operators and crypto-processor, protections/countermeasures against side channel attacks, cybersecurity/cyberdefense, ...

Hardware accelerators: arithmetic operators/accelerators on FPGAs, ASICs, GPUs and embedded multicores

Software libraries: arithmetic support for crypto and embedded systems, finite field arithmetic

VLSI design and CAD tools: ASIC and FPGA circuits, asynchronous circuits, low power consumption, circuit generation tools

Applications: embedded systems, digital security, cyber-security/defense, scientific computing, digital signal processing, image processing, digital control.

Current/Recent Professional Activities

2018: Chair of the organisation committee of CryptArchi 2018 (June, 17-20, Lorient, France)

2017+: Editorial Board of JOLPE: Journal of Low Power Electronics

2014+: Associate Editor of the IEEE Transactions on Computers

2014-2015: Program Committee co-Chair of the 22nd IEEE Symposium on Computer Arithmetic (ARITH-22)

Current/Recent Collaborations

2014-2017: Reliasic project with IRISA, Lab-STICC, IETR (funded by Labex CominLabs and Brittany Region)

2014-2017: H-A-H (Hardware and Arithmetic for Hyperelliptic Curves Cryptography) project with IRISA, IRMAR (funded by Labex CominLabs, Labex Lebesgue and Brittany Region)

Some recent presentations

Invited keynote at CRiSIS 2017 on Hardware Support for Physical Security (PDF slides)

Invited presentation at CEA NanoInnov (July 2017) on Arithmetic Tradeoffs on Performance/Cost/Security for Hardware Asymmetric Cryptography

Invited presentation at Colloque National du GDR SOC2 (June 2017) on Embedding Crypto in SoCs: Threats and Protections

Invited presentation at ECC (September 2015) on Hardware Accelerators for ECC and HECC

Some links

Symposia on Computer Arithmetic ARITH (main link), editions:

• 25 (June 2018, Ahmerst, MA, USA),
• 24 (July 2017, London, England),
• 23 (July 2016, Santa Clara, California, USA),
• 22 (June 2015, Lyon, France),
• 21 (April 2013, Austin, Texas, USA),
• 18 (June 2007, Montpellier, France),
• 14 (April 1999, Adelaide, Australia)

Seminars on Seminar on Security of Embedded Electronic Systems

Links to colleagues and groups

SAGE: a free open-source mathematics software system (book in french)

GDR du CNRS : IM - Arith - C2 / SoC-SiP / ISIS / Sécurité

ACM: digital library, conferences, publications, special interest groups [ SIGACT, SIGARCH, SIGBED, SIGDA, SIGMICRO, SIGSAC ]

IACR

IEEE: digital library, societies : [ CAS, CS, ITS, SSCS ]

Création du Groupe Thématique SMAI-MAIRCI

Société informatique de France (SIF)

Bulletin de la société informatique de France

Agence pour les mathématiques en interaction avec l'entreprise et la société (AMIES)

Workshops CryptArchi

Interstices (site de culture scientifique autour de l'informatique)

Images des mathématiques

Chercheur français, une espèce en voie de disparition ? / French researcher, a critically endangered species?

• Association SauvOnS la recherche

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Publications (Complete list / co-authors)

Some recent publications

• V. Migliore, M. Mendez, V. Lapotre, A. Tisserand, C. Fontaine and G. Gogniat. Hardware/Software co-Design of an Accelerator for FV Homomorphic Encryption Scheme using Karatsuba Algorithm. IEEE Transactions on Computers, pp. 335-347, vol. 67, n. 3, Mar. 2018 [DOI 10.1109/TC.2016.2645204] [HAL]
• J. Hormigo, J.-M. Muller, S. Oberman, N. Revol, A. Tisserand and J. Villalba-Moreno. Introduction to the Special Issue on Computer Arithmetic. IEEE Transactions on Computers, pp. 1991-1993, vol. 66, n. 12, Dec. 2017 [DOI 10.1109/TC.2017.2761278] [HAL]
• G. Gallin, T. O. Celik and A. Tisserand. Architecture level Optimizations for Kummer based HECC on FPGAs. presented paper at IndoCrypt, Chennai, India, Dec. 2017 [HAL PDF]
• G. Gallin and A. Tisserand. Hyper-Threaded Multiplier for HECC. presented paper at 51st Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, oct 2017. [HAL PDF]
• K. Bigou and A. Tisserand. Hybrid Positional-Residue Number System. paper presented at ARITH 22, Santa Clara, USA, July 2016. [HAL PDF]
• K. Bigou and A. Tisserand. Binary-Ternary Plus-Minus Modular Inversion in RNS. paper presented at IEEE Transactions on Computers, 2016. [HAL PDF]

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Students (Complete list)

Current PhD students

Libey Djath, (1st year/3), UBO Lab-STICC (grant DGA-PEC/UBO), co-advisor: K. Bigou

Gabriel Gallin, (4th year/4), CNRS IRISA Lab-STICC (grant HAH project)

Audrey Lucas, (3rd year/3), CNRS IRISA (grant DGA-PEC)

Geneviève Ndour, (2nd year/3), CEA LETI IRISA, co-advisor: A. Molnos

Timo Ziljstra, (1st year/3), CNRS Lab-STICC UBS (grant DGA-PEC/ARED), co-advisor: K. Bigou

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Software/Hardware

ECC Crypto-Processor

Free hardware processor for elliptic curve cryptography and its programming software [under development in the PAVOIS ANR project]

PACE

Prototyping Arithmetic in Cryptography Easily [collaboration with ARITH group LIRMM]

Seedgen

Seeds circuit generator (1/x and 1/sqrt(x)) [WWW]

MEPLib

Machine Efficient Polynomial Library [WWW]

Divgen

A divider unit generator : [WWW]

FLIP

Floating-Point Library for Integer Processors : [WWW]

On-line arithmetic library

VHDL on-line operators library (radix-2 representation)

Bibword

A minor Emacs mode for keywords in BibTeX files [WWW] beta version available

Links on softwares: AFUL

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Teaching / Enseignement (Archives)

Cryptology

Master 1 on Cyber-Security of Embedded Systems (CSSE in French), University South Brittany, Lorient, cryptology (approx 30h CM/TD/TP) 2017+ (course web site)

Organisation et cours d'écoles thématiques

Co-organisation et cours à l'école thématique ARCHI17 : Architectures des systèmes matériels enfouis et méthodes de conception associées (6-10 mars, 2017, Nancy)

Co-organisation et cours à l'école thématique ARCHI15 : Architectures des systèmes matériels enfouis et méthodes de conception associées (8-12 juin, 2015, Lille)     [ slides PDF: Processor Extensions for Security ]

Cours à l'école thématique ECOFAC2014 : Conception faible consommation pour les systèmes embarqués temps réel (19-23 mai 2014, Lorient)

Co-organisation et cours à l'école thématique ARCHI13 : Architectures des systèmes matériels enfouis et méthodes de conception associées (25-29 mars, 2013, Col-de-Porte)     [ slides PDF: Introduction to FPGA Circuits ]

Co-organisation et cours à l'école thématique ECOFAC2012 : Conception faible consommation pour les systèmes embarqués temps réel (21-25 mai 2012, La Colle-sur-Loup)

Co-organisation et cours à l'école thématique ARCHI11 : Architectures des systèmes matériels enfouis et méthodes de conception associées (2 - 6 mai, 2011, Mont-Louis)

Co-organisation et cours à l'école thématique ECOFAC2010 : Conception faible consommation pour les systèmes embarqués temps réel (29 mars - 2 avril, 2010, Plestin les Grèves, Côtes d'Armor)

Co-organisation et cours à l'école thématique ARCHI09 : Architectures des systèmes matériels enfouis et méthodes de conception associées (30 mars - 3 avril, 2009, Pleumeur-Bodou)

Co-organisation et cours à l'école thématique ARCHI07 : Architectures des systèmes matériels enfouis et méthodes de conception associées (19-23 mars, 2007, Boussens)

Organisation et cours à l'école thématique ARCHI05 : Architectures des systèmes matériels enfouis et méthodes de conception associées (21-25 mars, 2005, Autrans)

Co-organisation et cours à l'école thématique ARCHI03 : Architectures des systèmes matériels enfouis et méthodes de conception associées (31 mars - 4 avril, 2003, Roscoff)

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Contact

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Vitae

Short biography

Arnaud Tisserand, PHD 1997 and HDR 2010, is senior researcher ("directeur de recherche" in french) at CNRS (French National Center for Scientific Research) in computer science in Lab-STICC laboratory and the MOCS research group. His research interests include computer arithmetic, computer architecture, digital security, VLSI and FPGA design, design automation, low-power design and applications in applied cryptography, scientific computing, digital signal processing. He taught computer arithmetic, computer architecture and VLSI design. He was PC co-chair of ARITH-22 Symposium. He is Associate Editor of the IEEE Transactions on Computers. He is a senior member of the IEEE (SSCS, CAS) and member of the ACM and IACR.