Vianney Lapôtre

Associate professor at Université Bretagne Sud

International journal papers International journal papers

2020

C. Feron, V. Lapotre and L. Lagadec, "Automated Exploration of Homomorphic Encryption Scheme Input Parameters", Journal of Information Security and Applications (JISA), 2020.
Associate tool : PAnTHErS

M. A. Mukhtar, M. Mushtaq, M. K. Bhatti, V. Lapotre, G. Gogniat, "FLUSH + PREFETCH: A Countermeasure Against Access-driven Cache-based Side-Channel Attacks", Journal of Systems Architecture, vol 104, 2020

M. Mushtaq, J. Bricq, M. K. Bhatti, A. Akram, V. Lapotre, G. Gogniat, P. Benoit, "WHISPER A Tool for Run-time Detection of Side-Channel Attacks", IEEE Access, vol 8, pp. 83871-83900, 2020

A. Akram, M. Mushtaq, M. K. Bhatti, V. Lapotre, G. Gogniat, "Meet the Sherlock Holmes' od Side Channel Leakage: A Survey of Cache SCA Detection Techniques", IEEE Access, vol 8, pp. 70836-70860, 2020

M. Mushtaq, M. A. Mukhtar, V. Lapotre, M. K. Bhatti, G. Gogniat, "Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA", Information Systems, vol 92, 2020

2018

V. Migliore, M. Mendez Real, V. Lapotre, A. Tisserand, C. Fontaine, G. Gogniat, "Hardware/Software co-Design of an Accelerator for FV Homomorphic Encryption Scheme using Karatsuba Algorithm," in IEEE Transactions on Computers, vol.37, Issue.3, pp.335-347, 2018

M. Mendez Réal, P. Wehner, V. Lapotre, D. Göhringer and G. Gogniat, "Application Deployment Strategies for Spatial Isolation on Many-Core Accelerators", in ACM Transactions on Embedded Computing Systems (TECS), vol. 12, n. 2, Article 55, February 2018.

2017

V. Lapotre, G. Gogniat, A. Baghdadi, J.-P. Diguet, “Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding,” EURASIP Journal on Advances in Signal Processing, 2017.

V. Migliore, C. Seguin, M. Mendez Real, V. Lapotre, A. Tisserand, C. Fontaine, G. Gogniat, "A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm," ACM Transactions on Embedded Computing Systems (TECS), Volume 16 Issue 5s, 2017

2016

V. Lapotre, P. Murugappa, G. Gogniat, A. Baghdadi, M. Hubner, J.-P. Diguet, “A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.24, no.01, pp.383-387, Jan 2016.

International conference papers International conference papers

2020

G. Harcha, V. Lapotre, C. Chavet, P. Coussy, "Toward Secured IoT Devices: a Shuffled 8-Bit AES Hardware Implementation", in Proc. of 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

2019

M Mushtaq, A Akram, M.K. Bhatti, U. Ali, V Lapotre, G Gogniat, "Sherlock Holmes of Cache Side-Channel Attacks in Intel's x86 Architecture", in Proc. of IEEE Conference on Communications and Network Security (CNS), 2019.

2018

M. A. Wahab, P. Cotret, M. N. Allah, G. Hiet, A. Kumar Beswas, G. Gogniat, V. Lapotre, "A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components", in proc of Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2018.

M. A. Wahab, P. Cotret, M. N. Allah, G. Hiet, A. Kumar Beswas, G. Gogniat and V. Lapotre, "A small and adaptive coprocessor for information flow tracking in ARM SoCs", in proc of 2018 International Conference on Reconfigurable Computing and FPGAs (Reconfig), 2018.

M Mushtaq, A Akram, M.K. Bhatti, M. Chaudhry, V Lapotre, G Gogniat, "NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters", in Proc. of 7th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP), 2018.

M Mushtaq, A Akram, M.K. Bhatti, R.N. Bin Rais, V Lapotre, G Gogniat, "Run-time Detection of Prime+Probe Side-Channel Attack on AES Encryption Algorithm", in Proc. of Global Information Infrastructure and Networking Symposium (GIIS), 2018.

M Mushtaq, A Akram, M.K. Bhatti, M. Chaudhry, M. Yousaf, U. Farooq, V Lapotre, G Gogniat, "Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time", in Proc. of 25th IEEE International Conference on Electronics (ICECS), 2018.

C. Feron, V. Lapotre and L. Lagadec, "Fast Evaluation of Homomorphic Encryption Schemes based on Ring-LWE", in Proc. of 9th IFIP International Conference on New Technologies, Mobility & Security (NTMS), 2018.

2017

C. Feron, V. Lapotre and L. Lagadec, "PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption Schemes",14th International Joint Conference on e-Business and Telecommunications - Volume 6: SECRYPT, ICETE 2017, pages 359-366.

M. A. Wahab, P. Cotret, M. N. Allah, G. Hiet, V. Lapotre and G. Gogniat, "ARMHEx: A hardware extension for DIFT on ARM-based SoCs," in Proc. of 27th International Conference on Field Programmable Logic and Applications (FPL), 2017.

2016

M. A. Wahab, P. Cotret, M. N. Allah, G. Hiet, V. Lapotre and G. Gogniat, "Towards a hardware-assisted information flow tracking ecosystem for ARM processors," in Proc. of 26th International Conference on Field Programmable Logic and Applications (FPL), 2016.

M. Méndez Real, V. Migliore, V. Lapotre and G. Gogniat, “ALMOS many-core operating system extension with new secure-aware mechanisms for dynamic creation of secure zones,” in Proc. of 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2016.

M. Mendez Réal, V. Migliore, V. Lapotre, G. Gogniat, P. Wehner, and D. Göhringer, "Dynamic Spatially Isolated Secure Zones for NoC-based Many-core Accelerators", in Proc. of 8th IEEE International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2016.

M. Mendez Réal, V. Migliore, V. Lapotre, G. Gogniat, P. Wehner, J. Rettkowski and D. Göhringer, "MPSoCSim extension: An OVP Simulator for the Evaluation of Cluster-based Multicore and Many-core architectures", 4rd Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES) as part of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2016.

V. Migliore, M. Mendez Réal, V. Lapotre, A. Tisserand, C. Fontaine and G. Gogniat, "Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm", in proc of the 2016 International Conference on Field-Programmable Technology (FPT '16), Jianguo Hotel, Xi’an, China, 2016

2015

V. Migliore, M. Méndez Real, V. Lapotre, A. Tisserand, C. Fontaine and G. Gogniat, “Exploration of Polynomial Multiplication Algorithms for Homomorphic Encryption Schemes,” in Proc. of 2015 IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2015.

A. Butko, R. Garibotti, L. Ost, V. Lapotre, A. Gamatié, G. Sassatelli and C. J. Adeniyi-Jones "A Trace-driven Approach for Fast and Accurate Simulation of Manycore Architectures", 20th Asia and South Pacific Design Automation Conference (ASP-DAC'2015), 2015.

C. Effiong, V. Lapotre, A. Gamatié, G. Sassatelli, A. Todri and K. Latif, « On the Performance Exploration of 3D NoCs with Resistive-Open TSVs”, in Proc. of 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.

2014

A. Kologeski, F. Lima Kastensmidt, V. Lapotre, A. Gamatié, G. Sassatelli, A. Todri-Sanial, "Performance Exploration of Partially Connected 3D NoCs under Manufacturing Variability," in Proc. of 12th IEEE International New Circuits and Systems Conference (NEWCAS), 2014.

2013

V. Lapotre, P. Coussy, C. Chavet, H. Wouafo, and R. Danilo, “Dynamic branch prediction for high-level synthesis,” in 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013.

V. Lapotre, P. Murugappa, G. Gogniat, A. Baghdadi, M. Huebner, J.-P. Diguet, “Stopping-free dynamic configuration of a multi-asip turbo decoder,” in Proc. of 2013 16th Euromicro Conference on Digital System Design (DSD), 2013.

V. Lapotre, P. Murugappa, G. Gogniat, A. Baghdadi, M. Huebner, J.-P. Diguet, “A reconfigurable multi-standard asip-based turbo decoder for an efficient dynamic reconfiguration in a multi-asip context," in Proc. of 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013.

V. Lapotre, P. Murugappa, G. Gogniat, A. Baghdadi, J.-P. Diguet, J.-N. Bazin, M. Huebner, “Optimizations for an efficient reconfiguration of an asip-based turbo decoder,” in Proc. of 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013.

V. Lapotre, M. Huebner, G. Gogniat, P. Murugappa, A. Baghdadi, J.-P. Diguet, “An efficient on-chip configuration infrastructure for a flexible multi-asip turbo decoder architecture” in Proc. of 8th International Workshop on Reconfigurable Communicationcentric Systems-on-Chip (ReCoSoC), 2013.

P. Murugappa, V. Lapotre, A. Baghdadi, M. Jezequel, "Rapid Design and Prototyping of a Reconfigurable Decoder Architecture for QC-LDPC Codes," in Proc. Of 2013 IEEE International Symposium on Rapid System Prototyping (RSP), 2013.

2012

V. Lapotre, G. Gogniat, J.-P. Diguet, S. Haddad, A. Baghdadi, “An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding,” in Proc. of 2012 IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012.

National journal papers National journal papers

2013

V. Lapotre, P. Coussy, and C. Chavet, “Introduction de la prédiction de branchement dans la synthèse de haut niveau,” Technique et Science Informatiques, no. 2/2013, 281-301, 2013.

National conference papers National conference papers

2017

M. A. Wahab, P. Cotret, M. N. Allah, G. Hiet, V. Lapotre, G. Gogniat, "ARMHEx: a hardware extension for information flow tracking on ARM-based platforms", Les Rendez-Vous de la Recherche et de l’Enseignement de la Sécurité des Systèmes d’Information (RESSI 2017), 2017.

2016

M. Méndez Real, V. Lapotre, G. Gogniat and V. Migliore, "Physical isolation against cache-based Side-Channel Attacks on NoC-based architectures", Compas'2016.

V. Migliore, M. Méndez Real, V. Lapotre and G. Gogniat, "Algorithmes pour le chiffrement homomorphe", Compas'2016.

2013

V. Lapotre, P. Murugappa, G. Gogniat, A. Baghdadi, J.-P. Diguet, “Plateforme multi-ASIP reconfigurable dynamiquement pour le turbo décodage dans un contexte multi-standard,” in Proc. of Gretsi, 2013.

2011

V. Lapotre, P. Coussy, and C. Chavet, “Prédiction de branchement dans la synthèse de haut niveau,” in Proc. of SYMPosium en Architectures, Saint Malo, 2011.

Invited talks Invited talks

2019

V. Lapotre, A Hardware/software co-design approach for security analysis of application behavior - Applications on Dynamic Information Flow Tracking , Journée "Nouvelles Avancées en Sécurité des Systèmes d'Information", Toulouse, 2019.

2018

V. Lapotre, Déploiement sécurisé d'applications au sein des architectures many-cœurs, FETCH 2018.

2017

V. Lapotre, Sécurité des objets, Workshop InS3pect - Ingénierie Systèmes de Services Sécurisés Pour objEts ConnecTé, Sophia Antipolis, 2017.

2014

"A Dynamically Reconfigurable Multi-ASIP Architecture for Multi-Standard and Multi-Mode Turbo Decoding", International Symposium on System-on-Chip, 2014.

Other communications Other communications

2018

M. Mushtaq, A. Akram, M. Bhatti, V. Lapotre, G. Gogniat, "Cache-Based Side-Channel Intrusion Detection using Hardware Performance Counters", 16th International Workshops on Cryptographic architectures embedded in logic devices, Lorient, France, 2018.

2017

M. A. Wahab, P. Cotret, M. N. Allah, G. Hiet, V. Lapotre, G. Gogniat, "ARMHEx: a framework for efficient DIFT in real-world SoCs," 27th International Conference on Field Programmable Logic and Applications (FPL), 2017.

G. Bonnoron, C. Fontaine, G. Gogniat, V. Herbert, V. Lapotre, V. Migliore, A. Roux-Langlois,"Somewhat/Fully Homomorphic Encryption: Implementation Progresses and Challenges", In: El Hajji S., Nitaj A., Souidi E. (eds), Codes, Cryptology and Information Security. C2SI 2017. Lecture Notes in Computer Science, vol 10194. Springer, Cham, 2017

2015

C. Dévigne, J-B. Bréjon, Q. Meunier, F. Wajsbürt, M. Mendez Real, V. Migliore, V. Lapotre, G. Gogniat, M. Aichouch, M. Ait Hmid, C. Mancillas López, L. Bossuet, V. Fischer, "Applications security in manycore platform, from operating system to hypervisor: how to build a chain of trust", CHES 2015 Workshop on Cryptographic Hardware and Embedded Systems, 2015.

V. Migliore, M. Méndez Real, V. Lapotre, G. Gogniat, A. Tisserand, C. Fontaine, "Exploration of the best polynomial multiplication algorithm for homomorphic encryption schemes", CHES 2015 Workshop on Cryptographic Hardware and Embedded Systems, 2015.

V. Migliore, M. Méndez Real, V. Lapotre, G. Gogniat, A. Tisserand, C. Fontaine, "Somewhat homomorphic encryption schemes: which candidates and which expectations to have with this type of encryption schemes?", 13th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices, 2015.

2014

R. Garibotti, L. Ost, A. Gamatié, V Lapotre, C. J. Adeniyi-Jones and G. Sassatelli, "Multithreading for Compute Accelerators Through Distributed Shared Memory Design", Design Automation Conference (DAC'2014), Work-in-Progress Session, 2014.

PhD Thesis PhD Thesis

V. Lapotre, Toward dynamically reconfigurable high throughput multiprocessor Turbo decoder in a multimode and multi-standard context, thèse de doctorat, Université de Bretagne Sud, Lorient, Novembre 2013