Dominique HELLER
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Address: Laboratoire Lab-STICC Université de Bretagne Sud UBS Centre de Recherche, BP92116 56321 Lorient Cedex France Phone: +33-(0)2
97 87 46 25 Fax: +33-(0)2
97 87 45 27 E-mail: dominique.heller@univ-ubs.fr Citizenship: French |
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PROFESSIONAL EXPERIENCE
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- 1999-present: |
Research Engineer, Université de Bretagne-Sud UBS Lorient, Sciences and Techniques Department Lab-STICC UMR6285, CNRS |
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- 1998/99: |
Post-doc (University of Nantes, Laboratory : M.C.S.E) : Development of a Codesign tool “Cofluent Studio” (https://www.intel.fr/content/www/fr/fr/cofluent/overview) |
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EDUCATION
D.Sc. in Electrical
Engineering, Jan. 1998
University of Nantes, Laboratory : M.C.S.E. (Polytech’Nantes)
Nantes, 44, France,
Dissertation: " Performances modeling and evaluation for co-design”
Advisor: Dr. Jean Paul Calvez (University of Nantes/MCSE)
M.Sc. in Electronic
Science, 1992
University of Nantes, Laboratory : M.C.S.E. (Polytech’Nantes)
Nantes, 44, France,
Dissertation: "RTL code generation for performance model of the MCSE methodology“
Advisor: Dr. Jean Paul Calvez (University of Nantes/MCSE)
Engineering
degree in Electronic and Digital Technologies, 1992
Polytech Nantes, engineering school of University of Nantes
Nantes, 44, France,
GRADUATED STUDENTS
Former PhD-Student
· Ludovic Chavalarias (2024-)
Real-time analysis of ultra-high-speed network traffic using artificial intelligence tools
· Yann Bellec (2024-)
Detection, classification and tracking of acoustic targets by on-board artificial intelligence: application to fisheries
· Alexandre Foucher (2023-)
Obstacle
avoidance and collaborative work for marine surface drones
· Thomas Barguil (2020-2023)
Application of reinforcement learning methods to improve the QoS of audio calls on IP network
· El Mehdi Abdali (2016-2020)
·
Youenn Corre (2009-2012)
Automated Generation of Heterogeneous Multiprocessor Architectures: Software
and Hardware Aspects
Current Teaching
· Networks, Co-Design, Computer Vision, High Level Synthesis, Embedded Linux (Master)
RESEARCH INTERESTS
My research activity deals
with High-Level Synthesis
(http://www.gaut.fr), computer vision
in embedded systems, embedded linux, hardware/software codesign, high performance reconfigurable
architecture, UAV, USV and
Autonomous Systems.
RESEARCH PROJECTS
Several fundings support my research activity: CNRS, RNRT, RNTL, DGE, FUI, ANR, Private contracts, FEAMP
·
MABIMOUV (2025): MArine BIomass Megafauna mOnitoring Unmmaned Vehicle
Sponsor: GIS EMYN, , Academic
Partner : LIS, UMR 7020 , Industrial Partners: SEAPROVEN/FBV Marine, THALOS, RBR
· Dolfia (2024-2027): AUV-Based Side-Scan Sonar Real-Time Deep Learning Method for Underwater-Target Detection : Pipeline, cable and mine
Sponsor: AID (ANR MATHILDE), Industrial Partners: SEABER
·
GPA2M (2023-2025): Geo-Positioning by Landmarks in the Maritime Environment
Sponsor: AID, Academic
Partners: ENSTA
·
Exavision (2023-2024): Multiple UAV detection and tracking on embedded device
Sponsor: Private contract,
Industrial Partner: Exavision
·
Pontos (2021-2022): Project
for tools of number, size and weight measurement of species.
Sponsor: Feamp,
Région Bretagne, Lorient Agglomeration, Industrial Partners: Thalos
·
Surcouf (2021-2022): Smart Unmanned suRface
vehicle Cooperation for Ocean sUrveillance on Foils.
Sponsor: Région Bretagne, Lorient Agglomeration, Industrial Partners: IMSolutions, SEAir
·
Odessa (2020-2023): Marine object detection and tracking
Sponsor: Région Bretagne, Academic Partner: IMT ATlantique
Industrial Partners:
Inpixal, Exavision
·
Wavetel (2018): Network load balancer at 100 Gb/s (FPGA
Xilinx Utra-Scale+).
Sponsor: Private contract, Industrial
Partner: Wavetel
·
HPEC, (2015-2019): High Performance Embedded Computing:
UAV Case Study
Sponsor: Agence Nationale pour la Recherche ANR, Industrial Partner: InPixal
Academic Partners: INRIA Rhône-Alpes / Ctrl-A (Grenoble), Institut Pascal / DREAM (Clermont-Ferrand), Gipsa-Lab / SYSCo (Grenoble)
·
RubiSoft (2015): Code
optimization for radar signal processing
Sponsor: Private contract, Industrial Partner: RubiSoft
·
TSUNAMY (2013-2017): Secure cluster of a manycore architecture
Sponsor: Agence Nationale pour la Recherche ANR, Industrial Partner: CEA LIST
Academic Partners: Laboratoire Hubert Curien, UMR CNRS 5516, LIP6
CNRS UMR 7606
·
SWARMS (2013-2015): Reconfigurable Computing in UAVs
Sponsor: CNRS PICS, Academic Partner: ARCCA / QUT (Brisbane, Australia)
·
Astrium ST (2011/2012/2013):
High Level Synthesis and image processing on FPGA
Sponsor: Private contract, Industrial Partner: Astrium Space
Transportation
·
PROJECT P (2011-2014), framework for model-driven engineering of
embedded real-time systems, Sponsor: FUI project, Academic Partners:
UPS-IRIT, INRIA, ENPC
Industrial Partners:
Continental, AdaCore,
Airbus, Astrium, Rockwell Collins, Sagem, Thales Avionics, Aboard,Thales
Alenia Space, Atos, ACG Solutions, Altair, Scilab, STI, ONERA
·
SOCKET (2008 – 2011): SoC toolKit for critical Embedded sysTems
,
Sponsor: Direction Générale des Entrprises
DGE, Academic partner: INPG-TIMA, UPS-IRIT.
Industrial partners: Airbus,
Astrium, CNES, STMicroelectronics,
Thales R&T, Schneider Electric Industries, PSI-S, CEA-LETI, Magilem Design Services,
·
SOCLIB (2006 – 2009): An open platform for virtual prototyping of multi-processors
system on chip, Sponsor: Agence Nationale
pour la Recherche ANR,
Industrial partners: STMicroelectronics, Thales Communication, Thomson R&D, Silicomp, Magilem Design Services, TurboConcept, CEA-LIST, CEA-LETI
Academic
partner: CITI, Telecom Paris Tech, INRIA Futurs,
IRISA, UPMC-LIP6, INPG-TIMA, LIS,
LISIF, UBS-LabSTICC
·
ONAGRE
(2005 – 2008): envirOnnement de coNception et de prototypAGe
d'applications Radio et mobilE , Sponsor:
France Telecom R&D, Industrial partners: France
Telecom R&D
·
SystemC’Mantic (2003 – 2005): A high level Modelling and Co-Design
Framework
Sponsor: RNTL (Réseau National de recherche et
d'innovation en Technologies logicielles),
Industrial partners: Thales Communication, CEA-LIST, Prosilog, Academic partner: INPG-TIMA
·
ALIPTA (2002 –
2004): Algorithmic Level IP for Telecom Applications
Sponsor: RNRT (Réseau National de Recherche en
Télécommunications),
Industrial partners: Thales Communication, CEA-LIST, SACET, TNI-Valiosys, TurboConcept
Academic
partner: ENST-Bretagne
· EPICURE (2001-2003): Co-design methodology and tools
Sponsor: RNTL (Réseau National de recherche et
d'innovation en Technologies logicielles),
Industrial partners:, Esterel technologie, Thales Communications, I3S, CEA LIST
·
MILPAT (1999-2001):
Semantics controls and rules for High Level Synthesis Algorithms
Sponsor: RNRT (Réseau National de Recherche en
Télécommunications),
Industrial partners: Thales
Communication, SACET, TurboConcept
Academic
partner: ENST-Bretagne
PUBLICATIONS
Book chapters
P. Coussy, C. Chavet, P. Bomel, D. Heller, E. Senn, E. Martin
GAUT: A
High-Level Synthesis Tool for DSP applications, “High-Level Synthesis: From
Algorithm to Digital Circuits”,
Springer,
Journals
C. Hireche, C. Dezan, S. Mocanu, D. Heller and J-Ph. Diguet,
Context/Resource-Aware Mission Planning Based on BNs and Concurrent MDPs for
Autonomous UAVs, Sensors. 18(12):4266, Dec. 2018, https://doi.org/10.3390/s18124266
Youenn Corre, Jean-Philippe Diguet, Dominique Heller,
Dominique Blouin, Loïc Lagadec. TBES: Template-Based Exploration and Synthesis of Heterogeneous
Multiprocessor Architectures on FPGA.
ACM Transactions in Embedded Computing Systems,
Association for Computing Machinery (ACM), ol. 15
Issue 1, Article. No. 9, Jan. 2016..
F.
Thabet, P. Coussy, D. Heller, E. Martin
“Exploration
and Rapid Prototyping of DSP Applications using SystemC
Behavioral Simulation and High-Level Synthesis”, Journal of Signal Processing Systems, 2009
P. Coussy, G. Le Breton, D. Heller
“Multiple
Word-Length High-Level Synthesis”, EURASIP
Journal on Embedded Systems, 2008
Y. LE MOULLEC, D. HELLER,
J.P. DIGUET, J.L. PHILIPPE
"Estimation du parallélisme au niveau système pour
l'exploration de l'espace de conception de systèmes enfouis",
Technique
et Science Informatiques (RSTI-TSI), Vol. 22, n°3/2003, pp. 315-349, Lavoisier Hermes-Science
publications
J.P. CALVEZ, O. PASQUIER,
D. HELLER
"Conception
conjointe matériel-logiciel des systèmes basée sur la méthodologie MCSE".
Chapitre dans "Conception conjointe des systèmes matériels et
logiciels", pp 10-52,
Collection
CTST, Editeurs: J.M. Bergé, J. Courvoisier. Edition Eyrolles 1998.
J.P. CALVEZ, O. PASQUIER, D. HELLER
"Hardware/Software
System Design Based on the MCSE methodology". Chapitre
dans "Current Issues in Electronic Modeling",
Vol 9 - System Design, pp 1-36. Editeurs: J.M. Bergé, O. Levia, J. Rouillard.
Edition Kluwer Academic Publishers, Mars 1997.
Conferences
T. Marques, D. Heller, C. Seguin and J. Laurent, " Low Cost AI Based Detection of Floating Objects Using Stereo Cameras and Radar" , The 25th Chesapeake Sailing Yacht Symposium, March 2025, Annapolis, MaryLand.
R. Douguet, A. Foucher, Y. Eustache, D. Heller and J. Laurent, "Cooperative docking system for Unmanned Surface Vehicle (USV)," OCEANS 2024 - Halifax, Halifax, NS, Canada, 2024
R. Douguet, D. Heller, J. Laurent,, “ Multimodal perception for obstacle detection for flying boats - Unmanned Surface Vehicle (USV) ”, OCEANS 2023 IEEE, Limerick
J. Sharafaldeen, M. Rizk, D. Heller, A. Baghdadi and J-Ph. Diguet, “Marine Object Detection Based on Top-View Scenes Using Deep Learning on Edge Devices”, in proc.of the the IEEE International Conference on Smart Systems and Power Management (IC2SPM), November, 2022
Mostafa Rizk, Dominique Heller, Ronan Douguet,
Amer Baghdadi, Jean-Philippe Diguet. Optimization of
Deep-Learning Detection of Humans in Marine Environment on Edge Devices.
ICECS 2022: IEEE International Conference on Electronics Circuits and Systems, Oct 2022, Glasgow, United Kingdom.
Dominique Heller, Mostafa Rizk, Ronan Douguet, Amer Baghdadi, Jean-Philippe Diguet. Marine Objects Detection Using Deep Learning on Embedded Edge Devices.
IEEE International Workshop on Rapid System Prototyping (RSP), part of Embedded Systems Week (ESWEEK), Oct 2022, Shanghai (virtual), China.
Thomas Barguil, Johann Laurent, Nicolas Bohelay, Dominique Heller. Anomaly Detection Algorithm for Acoustics Phenomena.
The 2021 World Congress in Computer Science, Computer Engineering, & Applied Computing (CSCE'21), Jul 2021, Las Vegas, United States.
E. Moréac, E. M. Abdali, F. Berry, D. Heller, J-Ph. Diguet, Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV,
31st Int. Workshop on Rapid System Prototyping (RSP), ESWeek, Virtual Conference, Sep. 2020.
J. Mazuet, I-H. Atchadam, D. Heller, C. Dezan, M. Narozny and J-Ph. Diguet, QoS driven dynamic partial reconfiguration: Tracking case study,
ReCoSoC, Jul 2019, York, United Kingdom.
S. Mak-Karé Gueye, G. Delaval, E. Rutten, D. Heller and J-Ph. Diguet, "A Domain-specific Language for Autonomic Managers in Hardware Reconfigurable Architectures",
15th IEEE Int. Conf. on Autonomic Computing
(ICAC), Trento, Italy, Sep., 2018.
El Mehdi Abdali, M. Pelcat, F. Berry,, J-Ph. Diguet, D. Heller, Task Clustering Approach to Optimize the Scheduling on a Partially Dynamically Reconfigurable FPGAs for image processing algorithms,
ICDSC '16, New York, USA, 2016.
Self-Adaptive HW/SW Architecture for Unmanned Aerial Vehicles (UAVs)".
Sara Zermani (UBO), Hanen Chenini (UBO), Catherine Dezan (UBO), Reinhardt Euler (UBO), Dominique Heller (UBS), Jean-Philippe Diguet (CNRS), Duncan Campbell (QUT), Brendan Chen (QUT), Gilles Coppin (TB).
Presented at GDR SOC-SIP (Nantes, june 2016) and at Computer Sciences PhD Seminar (SIP, April 2016).
H. Chenini, D. Heller, C. Dezan, J-Ph. Diguet, D. Campbell, Embedded Real-Time Localization of UAV based on an Hybrid Device,
IEEE ICASSP, Brisbane, Australia, April 2015.
Mickael Lanoe, Matteo Bordin,
Dominique Heller, Philippe Coussy, Cyrille Chavet:
A modeling and code generation framework for critical embedded systems design:
From Simulink down to VHDL and Ada/C code.
ICECS 2014: 742-745
Y. Corre, J.P. Diguet, L. Lagadec, D. Heller and D. Blouin. “Fast Template-based Heterogeneous MPSoC Synthesis on FPGA”.
In Applied Reconfigurable Computing 2013 (ARC 2013), Los Angeles (USA), 2013
Youenn Corre, Van-Trinh Hoang, Jean-Philippe Diguet, Dominique Heller, Loïc Lagadec,
"HLS-based Fast Design Space Exploration of ad hoc hardware accelerators:
a key tool for MPSoC Synthesis on FPGA",
DASIP 2012, October 23-25, 2012 Karlsruhe, Germany
Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy and Luca Benini
“OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters”,
DSD 2012, Sept 2012, Izmir, Turkey
Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy and Luca Benini
"OpenMP-based Synergistic
Parallelization and Hardware Acceleration for On-Chip Multi-Core Shared-Memory
Clusters",
2012
DAC, Work-In-Progress Session. June 3-7, San
Francisco, USA
Y.Corre,
J-Ph. Diguet, D.Heller, L.Lagadec
“A Framework for
High-Level Synthesis of Heterogeneous MP-SoC”,
22nd ACM Great
Lake Symposium on VLSI (GLSVLSI), Poster,
Salt Lake City, USA, May 2012.
P. Coussy, D. Heller, and C. Chavet
"High-Level
Synthesis: On the Path to ESL Design",
In Proceedings of the 9th International
Conference on ASIC (ASICON 2011),
Xiamen, China.
G. Lhairech-Lebreton, P. Coussy, D. Heller, E. Martin
“Bitwidth-Aware High-Level Synthesis for Designing Low-Power
DSP Applications”,
IEEE
International Conference on Electronics, Circuits, and Systems (ICECS), 2010
Farhat Thabet, Philippe
Coussy, Dominique
Heller, Eric Martin:
Exploration and Rapid Prototyping of DSP Applications using SystemC
Behavioral Simulation and High-level Synthesis.
Signal
Processing Systems 56(2-3): 167-186 (2009)
Thabet F., Coussy P., Heller D., Martin E.
“Behavioral Description Model BDM for Design Space
Exploration: a Case Study of His Algorithm for MC-CDMA System”,
European Signal Processing Conference (EUSIPCO), 2007
F. THABET, D. HELLER, P. COUSSY, E. Martin
"Design
Space Exploration of DSP Applications Based on Behavioral
Description Models ",
SIPS’2006, October 2006,
L. Kriaa, S. Adriano, E. Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, P.
Coussy, E. Martin, Heller D., Tabet F. et al
“SystemC'mantic : A high level Modeling and Co-design Framework For Reconfigurable Real
Time Systems”,
Forum on Design Languages FDL, 2005
Y. LE MOULLEC, J.P.
DIGUET, D. HELLER , J.L. PHILIPPE
"Fast and Adaptive Data-flow and
Data-transfer Scheduling for Large Design Space Exploration ",
ACM/SIGDA
GLSVLSI02,
J-P. Calvez, D. Heller, F. Muller, O. Pasquier
Modélisation et évaluation d architectures avec l outil MCSE ToolBox.,
2ème Conférence Annuelle d Ingénierie Système,Toulouse, 26-28 juin 2001
O. Pasquier, F. Muller, J-P. Calvez, D. Heller,
"The MCSE approach for System-Level-Design",
FDL 99,
Workshop on System Specification & Design Languages, Lyon, 30 Aout-3 Septembre 1999
J.P. Calvez, D. Heller, F. Muller, O. Pasquier
A
Programmable Multi-Language Generator for CoDesign,
Poster for DATE’98,
J.P. CALVEZ, D. HELLER,
O. PASQUIER
"Uninterpreted
Co-Simulation for Performance Evaluation of Hw/Sw Systems",
CODES/CASHE’96,
4th International Workshop on Hardware/Software Co-Design,
J.P. CALVEZ, D. HELLER,
O. PASQUIER
"System
performance modeling and analysis with VHDL: Benefits
and limitations",
VHDL-FORUM EUROPE Spring’95 Working Conference, IRESTE,
J.P. CALVEZ, D. HELLER, P. BAKOWSKI
"Functional-level
synthesis with VHDL"
EURO-VHDL'93, 20-24 Septembre 1993, Hambourg.
D. HELLER,
P. ADAM, J.P. CALVEZ
"A DC
motor Controller ASIC implemented by synthesis of a VHDL description"
EDAC-EUROASIC 93, 22-25 Février 1993, Paris.