Satyajit Das

Postdoctoral Researcher | satyajit.das@univ-ubs.fr

ABOUT

I am a postdoc researcher at the Lab-STICC, Université Bretagne Sud. My research interests span the areas of architecture, methods and tools for embedded systems, including CGRAs, custom processors, multi-cores, high-level synthesis and compilers. The main focus of my research is to implement highly energy efficient solutions digital architectures in the domain of heterogeneous and reconfigurable multi-core System on Chips (SoCs). This includes architectures, design implementation strategies, runtime and compilation support to address performance, energy efficiency for both high-end embedded platforms and ultra-low-power computing platforms targeting the IoT domain.

DOWNLOAD CV

Latest news! PhD Thesis is accepted for poster presentation at DATE 2019 PhD Forum. Paper entitled "Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs" is accepted for full presentation at DATE 2019.
EDUCATION

Ph.D. in Electronics and Computer Engineering
Université Bretagne Sud, France; University of Bologna, Italy
"Architecture and Programming Model Support For Reconfigurable Accelerators in Multi-Core Embedded Systems"

GRADUATED IN JUNE 2018


WORK

Postdoctoral Fellow
Lab-STICC, Centre de Recherche Christiaan Huygens, France

An Energy-Efficient and Flexible Solution for Near-Sensor Ultra-Low Power Secured Processing in Microcontroller-based IoT devices

JUNE 2018 - CURRENT

Visiting Researcher
Lab-STICC, Centre de Recherche Christiaan Huygens, France

A Diffie Hellman reconfigurable security architecture in NOC based MPSoCs

APRIL 2014 - AUGUST 2014

Senior Research Fellow
CR Rao Advanced Institute of Mathematics, Statistics and Computer Science, Hyderabad, India

Design and Implementation of an Indigenous Block Cipher

Side Channel Cryptanalysis

AUGUST 2012 - MARCH 2014


Research Interests

Energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi-core SoCs. This includes architectures, design implementation strategies, runtime support and compilation support to address performance, energy efficiency for both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain


Publications

Google scholar link


Github Link

This contains SystemVerilog implementation of the CGRA referred to as Integrated Programmable Array(IPA), with the support to augment with the open source PULP multi-core platform. This also contains the description of the APIs to control the IPA from a single core.


Ultra Low Power Platforms

IPA

Integrated Programmable Array (IPA) is a Coarse Grained Reconfigurable Array(CGRA) based ultra-low power accelerator for near sensor data processing. It possesses the cabaility to accelerate arbitrary number of loops and conditiobnal in the applications. In this context of acceleration the IPA is a class itself. The recent paper on the IPA architecture and its compilation approach can be found here.

reconfigurable accelerator

PULP

The Parallel Ultra Low Power (PULP) Platform started as a joint effort started by ETH Zürich and University of Bologna in 2013 to explore new and efficient architectures for ultra-low-power processing. The efficient implementations of RISC-V cores (both 32 and 64 bit), peripherals and complete systems from simple micro-controllers, to state-of-the art OPENPULP release which sets a new bar for low-power multicore processor for the IoT on the GitHub page.

multi-core platform



CONTACT

Email
satyajit.das@univ-ubs.fr, satyajit.das@unibo.it

Adress
Lab-STICC - Centre de recherche
Université de Bretagne Sud
56325 Lorient Cedex

Phone
+55 8933-2383

SOCIAL LINKS