EDA Software Releases

GAUT (web site)

 Open Source high-level synthesis tool

 Automatic generation of an RTL architecture from a C/C++ specification

 http://lab-sticc.fr/www-gaut

 More than 100-150 downloads/year since 2007from more than 60 countries.

DsxPlore

 Exploration and Rapid Prototyping of DSP Applications

 SystemC behavioral simulation & High-Level Synthesis

STAR

 Generation of space time adapters

 Automatic synthesis of parallel interleaver architectures

 IP-core integration


Research Projects

SPICA          2015-2019, FUI Project, STMicroelectronics, Dolphin, TIMA, Lab-STICC

SENSE         2013-2016, Brittany county, Lab-STICC (UBS, Telecom Bretagne), IRISA

Astrium ST-2            2013, Private contract, Lab-STICC, Astrium Space Transportation

MPPA          2013, Private contract, Lab-STICC, Kalray

GIGADEC   2011-2013, Brittany county, Lab-STICC (UBS, Telecom Bretagne), Turbo-concept

Astrium ST  2011/2012, Private contract, Lab-STICC, Astrium Space Transportation

Projet P        2011-2013, FUI project, Aboard Engineering, AGC Solutions, AdaCore, Airbus, Altair, ASTRIUM, ATOS Origin, Continental, Ecole des Ponts ParisTech, INRIA/Aoste-Espresso-Metalau, IRIT/INPT/ENSEEIHT, Lab-STICC, ONERA, Rockwell Collins, Sagem Défense Sécurité, Scilab, ST Informatique Services, Thales Alenia Space, Thales Avionics

SoCKET      2008 – 2011, FUI project, Airbus, Astrium, CNES, STMicroelectronics, Thales R&T, Schneider Electric Industries, PSI-S, CEA-LETI, Magilem Design Services, INPG-TIMA, UPS-IRIT, UBS-LabSTICC

SocLib          2006-2009, ANR/RNTL platform, STMicroelectronics, Thales Communications, Thomson Silicon Components, Prosilog, TurboConcept, Silicomp, UPMC/LIP6, ENST, UPMC/LISIF, CEA LIST, INRIA Futurs, IRISA, LESTER/Lab-STICC, IETR INSA, TIMA, CEA LIST, CITI

FLASH        2006-2007, ARC INRIA, IRISA, LIFL, LESTER, INSERM U694

Onagre         2005-2008, CRE France Telecom, France Telecom, LESTER/Lab-STICC

ANTELOP  2005, PRIRE, Lab-STICC

SystemC’Mantic       2003-2005, RNTL project, Thales communications, TIMA, CEA LIST, TIMA, LESTER

ALIPTA      2002-2004, RNRT project, Valiosys, Thales, Sacet, Turbo-Concept, ENST Bretagne

 

Patents

« Architecture de réseau de neurone, procédé d'obtention et programmes correspondants », FR1261155 / R21609WO, December 2012

« Système de traitement de données avec cache active », FR1256715, june 2012

« Dispositif auto-configurable d'entrelacement / désentrelacement de trames de données», FR1251688. February. 2012

“Self-configurable device for interleaving/de-interleaving data framesWO2013124449 A1, August 2013

Apparatus for data interleaving algorithm”, CNRS – STMicroelectronics U.S. Patent application 20090031094, January 29, 2009.

 « Procédé et dispositif d’entrelacement de données », CNRS – STMicroelectronics, Brevet Français n° 0754793 10, 30 April 2007.