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Student
Advising |
Current Ph.D. Students Robin Danilo Bio-inspired vision system based on binary sparse
neural networks Huges Wouafo Neuromorphic hardware architectures and sparse
neural coding Satyajit Das Architecture and programming model support for
reconfigurable accelerators in shared-memory many-cores Ph.D.
Graduates Thomas Peyret High-Level Synthesis for designing fault tolerant
architectures on FPGA, Mohamed Ben Hamouda High level synthesis for circuit generation that
supports software like debugging Saeed Ur Remhan Toward Flexible Hardware Architectures for Parallel
Turbo-like Decoders. Paolo Burgio Use of shared memory in the context of embedded
multi-core processor: exploration of the technology and its limits Aroua Briki Architectural Synthesis for designing complex memory
unit Awais Sani, Algorithm / Architecture Matching for the design of
complex memory pattern-access for Digital Signal Processing applications Ghizlane Lebreton-Lhairech,
High-Level Synthesis for low-power design on FPGA Kods Trabelsi, Optimization methods for the hardware design of
digital systems Caaliph Andriamisaina, High-Level Synthesis of multimode Architecture for
DSP applications Cyrille Chavet, High-Level Synthesis of Space and Time Communication
Adpater Farhat Thabet Behavioral Modeling for the Simulation and the
High-Level Synthesis of Algorithmic IP Core M.Sc.
Graduates Baptiste Goupille-Lescar Design and programmation
of reconfigurable accelerators in shared-memory many-cores Sureshbabu Ramesh Study and analysis of
application mapping methods on CGRAs Robin Danilo Architecture and Programming Model Support for
Efficient Heterogeneous Computing on Tigthly-Coupled
Shared-Memory Clusters Nicolas Charpentier Neuromorphic hardware architectures and sparse
neural coding Hugues Wouafo HLS tool based on LLVM front-end Michelle Furtado Pinheiro Do Carmo Virtual prototyping of an MP3 codec with the SocLib platform Vianney Lapotre Branch prediction for high-level synthesis Aroua briki Hierarchical High-Level Synthesis: A Case study of a
Reed Solomon Encoder-Decoder Hicham Lalaoui Hassani Impact study of the HLS design steps and RTL coding
styles on the design optimization Mickael Adam Design Space Exploration for MPSoC Moahamed Aabidi Design with HLS : A case study of a Maximum A
Posteriori for Turbo decoder Ghizlane LeBreton, Bit-Width Aware High-Level Synthesis Youcef Mekla High-Level Synthesis for Low-Power Design Sebastien Tregarot Fast Prototyping of a MIMO application using the SocLib simulation platform Communication refinement for the simulation and the
synthesis of algorithmic IP-core Post-doc
researchers Awais Sani Auto-configurable Hardware Architectures for
Parallel Turbo-like Decoders Jorgiano Vidal HLS tool front-end Caaliph Andriamisaina Automatic generation of simulation model using HLS Engineers Ghizlane Lebreton GAUT3 : High-Level Synthesis tool Mickael Lanoe GAUT3 : High-Level Synthesis tool LinFeng Ye Parallel
interleaver generator |