Professional Services
Editorship
Organizer
- Organizer et Chair of the Tutorial on
High-Level Synthesis, IEEE Design Automation Conference DAC San Francisco, USA, July
26-31, 2009
- Co-organizer et Chair of the
international workshop “ High-Level
Synthesis: Next Step to Efficient ESL Design”, IEEE Asia and
South Pacific Design Automation Conference ASP-DAC, Yokohama, Japan, January
19-22, 2009.
- Co-organizer et Chair of the
international workshop “ High-Level
Synthesis: Back to the Future ”, IEEE Design Automation
Conference DAC Anaheim, USA, June 8-13, 2008.
- Co-organizer et Chair of the
international workshop “ The
New Wave of the High-Level Synthesis ”, IEEE Design and Test in Europe DATE Munich, Germany, March
10-14, 2008.
- Co-organizer et
Chair of the 1st ECSI-UBS international High-Level Synthesis Workshop, (in
conjunction with the Forum on Design Language FDL), Darmstadt, Germany, 2006 September 18.
Technical
Program Committee
Co-Chair
- IEEE Design and Test in Europe DATE, Topic D11 Architectural
and High-Level Synthesis (2010)
Member
- IEEE International Symposium on
Circuits and Systems ISCAS (2005, 2006, 2007, 2008, 2009, 2010)
- IEEE International Great Lake Symposium on VLSI GLSVLSI
(2007, 2008, 2009, 2010)
- French
MAnifestation des Jeunes Chercheurs STIC MajecSTIC (2006, 2007)
Reviewer
Journal
- IEEE Design and Test of
Computers
- IEEE Transactions on Computer
Aided-Design of Integrated Circuits and Systems (TCAD)
- ACM Transactions on Embedded
Computing System (ACM TECS)
- Integration, the VLSI Journal,
Elsevier Science
- Journal of Embedded Computing
(JEC)
- International Journal of
Circuits, Systems, and Computers (JCSC)
- EURASIP Journal on Embedded
Systems (JES)
Conference
- IEEE Design Automation and Test
in Europe (DATE)
- IEEE International Symposium on
Circuits and Systems (ISCAS)
- IEEE International Great Lake Symposium on VLSI (GLSVLSI)
- IEEE International Design
Automation Conference (DAC)
- MAnifestation des Jeunes Chercheurs STIC (MajecSTIC 2006, 2007)
- Journée
Francophone sur l'Adéquation Algorithme/Architecture (JFAAA 2002)
Society
membership
- OSCI Member : Key Contributor
in the Synthesis Working Group (SWG)
- IEEE member (Institute of Electrical and Electronics Engineers, Inc.)
- ECSI member (European
Electronic Chips & Systems design Initiative 2006-2009)
- Member of the CNRS Research
Group on Information, Signal, Images and ViSion GdR-ISIS
- Member of the CNRS Research
Group on System-on-Chip & System-In-Package GdR
SoC-SIP
- EURASIP European Association
for Signal Processing (2006-2008)