Philippe Coussy is a full professor in the Lab-STICC (CNRS) at the Université de Bretagne-Sud,
France, where he leads the “Design of Advanced Architectures”
group. He was graduated from
Université Pierre et Marie Curie (MSc, 1999),
Université de Bretagne-Sud (Ph.D., 2003 and Habilitation 2011). He
holds the scientific excellence fellowship (PEDR/PES A) since 2008. He is
member of the Advisory Board of the GDR on SoC-SIP
and chair of the topic “embedded software and hardware
architecture” since 2011. He is member of the Advisory Board of the GDR
on BioComp and chair of the topic “system
design” since 2015. He is a member of the technical committee of the IEEE
Signal Processing Society, Design and Implementation of Signal Processing
Systems (DISPS) since 2011. He is member of the European Network of Excellence HiPEAC. His research interests include system-level design
and methodologies, high-level synthesis, computer-aided design for SoCs, embedded systems, low-power design for FPGAs and
neuromorphic computing. He has supervised 16 PhD theses (5 in progress), 16
M.Sc. theses and published more than 60 papers in edited books, journals or
conference proceedings on these topics. He holds 5 patents in hardware design
domain. He has organized several workshops and tutorials in many outstanding
international conferences including DAC, DATE, CODES+ISSS and ASP-DAC. He was
guest editor for a special issue of Journal of Electrical and Computer
Engineering on “ESL Design Methodology” (2012), guest editor for a
special issue of IEEE Design and Test of Computer on “High-Level
Synthesis” (2009) and co-editor of the books “High-Level Synthesis:
From Algorithm to Digital Circuit” (Springer) (2008) and “Advanced
Hardware Design for Error Correcting Codes” (Springer) (2014). He has
been a member of the 2009 Catrene EDA roadmap and the
2011 HiPEAC roadmap committees. He regularly serves
as a national expert (ANR, MESR) and international expert (Canada, Israel,
Portugal…) participates as PC member in many international ACM/IEEE
conferences (DATE, ICASSP, ISCAS, ASAP, GLSVLSI, SIPS, DAC, FPL…) and as
reviewer for major journals (IEEE TCAD, TECS, JETCAS, D&T of Computers, ACM
TODAES, TECS…). He is Associate Editor of the IEEE Signal Processing
Letters for the Design and Implementation of signal processing systems
(HWD-ARCH), Programmable Hardware e.g. FPGA, SoC or
ASIC for DSP Algorithms (HDW-PROG) and Multicore
Processors for DSP Algorithms (HDW-MCORE).