Cedric Marchand


My picture

Research engineer at UBS (Universite de Bretagne Sud), Lorient, France, in the lab Lab-STICC (UMR 6285).

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Work experience

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Research and interest

My research area is in VLSI architectures and digital communications.

Current research areas:

Previous research areas:

  1. Trellis aggregation for high code rate turbo-code.
  2. Turbo-Code architecture
  3. Low Density Parity Check code: (more information in LDPC project).
  4. (2000-2002) White Gaussian Noise Generator for channel emulation (more information in WGNG project).

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Industry collaborations

  1. Decoding architecture for Cortex code (2011-2014)
  2. LDPC decoder architecture for DVB-S2 standard (2009-2011, 2013-2014)
  3. Go here for LinkedIn profile

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Publications

Go here for the list of publications (from ResearchGate)

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