High Speed Low Power Architecture For Memory Management in a Viterbi Decoder

Key words: VLSI, Viterbi algorithm, Trace-Back, Exchange Register, low power, path memory

Abstract:
The management of the surviving-path memory in the Viterbi algorithm is generally performed by Trace-Back or Exchange Register. It has been shown that combining these two techniques leads to efficient realisation [5-7]. In the present work, formal expressions of computational power, memory and latency are presented for several classes of algorithms. For a ?=4, L=64 Viterbi decoder, this formalism helps to find two algorithms that respectively reduce by a factor of 4 and 7 respectively, the computational power compared to a direct Exchange Register. Theoritical results and place&route netlist generated through VHDL synthesis are in concordance

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Authors: Emmanuel Boutillon, Nicolas Demassieux

Reference: ISCAS'96, IEEE, vol. 1, pp. p.284-7, Atlanta 1996.