Simplified Path Metric Updating in the M Algorithm for VLSI Implementation

Key words: VLSI, M algorithm, sorting, path extension

Abstract:
A VLSI structure for path metric updating in the M algorithm is presented. The architecture is based on the combination of a modified Batcher's odd-even merging network and a bitonic selection procedure. A property of the trellisstructure allows to replace an existing solution based on two 2M--itemsorting operations by three M-item sorting operations with an additionalone-layer bitonic merger. These three sorting networks and the bitonic merging procedure leads to a reduction of up to 50\% in hardware complexity.

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Authors: Luis Gonzalez, Emmanuel Boutillon

Reference: ICASSP'00, IEEE, Istenbul 2000.