------

WP3: Architectural study

The aim of this WP is to study, optimize and develop the hardware architecture of a NAN Decoder for Turbo-Code and LDPC code. The practical problems of internal precision, decoding scheduling, memory organization, pseudo noise generation and its utilization will be addressed. Two hardware demonstrators implementing NAN decoder (on FPGA) will be developed, one for Turbo-Code, the other one for LDPC code. Finally, fair comparisons in terms of performance versus complexity will be done between classical and new decoders.

------

Task 3.1 Architectural studies. [M6-M27]

The hardware implementation of a NAN-Decoder will be studied. Impact of architecture on performance will be obtained using result of WP2 to speed up the simulation.

  • Deliverable 3.1.a (Date: M15, Editor: Lab-STICC, Type: Report). Intermediate report on LDPC architecture. This deliverable has been merged with D3.2.a.
  • Deliverable 3.1.b (Date: M15, Editor: Turbo-concept, Type: Report). Intermediate report on Turbo-Code architecture.
  • Deliverable 3.1.c (Date: M27, Editor: Lab-STICC, Type: Report) Final report on LDPC architecture. This deliverable has been merged with D3.2.a.
  • Deliverable 3.1.d (Date: M27, Editor: Turbo-concept, Type: Report) Final report on TurboCode architecture. This deliverable has been cancelled.

    ------

    Task 3.2 (M28-M34, VHDL and report): Hardware Implementation. [M28-M34]

    The objective of this task is to do the hardware implementation of a classical and a NAN-Decoder for a LDPC code (the selection of the code will be done later) and integration of the decoder inside an emulation environment.

  • Deliverable 3.2.a (Date: M34, Editor: Lab-STICC, Type: VHDL and report) Result of hardware emulation of a LDPC code, report comparing pro - cons of NAN Decoder versus classical decoder.
  • Deliverable 3.2.b (Date: M36, Editor: CEA-LETI, Type: Report) Result of hardware emulation of a LDPC code, report comparing pro and cons of randomized bit-flipping decoders (memory-enhanced PGDBF and syndrome-based bit-flipping) versus classical decoder.

    ------

    Task 3.3: Digital vs Analog noise generation [M33-M36]

    The objective of this task is to compare in terms of complexity and quality technique to generate digital and analog noise.

  • Deliverable 3.3 (Date: M36, Editor: Lab-STICC, Type: report) Noise generation. Comparison between digital and analog noise generation. This deliverable has been cancelled.

    ------

    Task 3.4 (VHDL and report): Hardware Implementation. [M40-M45]

    The objective of this task is to propose and evaluate the hardware complexity of the Array Code decoder.

  • Deliverable 3.4 (Date: M40, Editor: Lab-STICC/UBS, Type: Report) Architecture and complexity estimation of an Array code decoder.