The objective of the NAND project is to improve the performance of an iterative decoder by a "smart injection" of randomness inside the decoding process.
The performance obtained from an efficient implementation of error control codes is one of the key elements that makes the difference within competition. The important features that make a product successful can be either low complexity, low energy consumption, or low error probability performance. The three companies involved in the NAND project, STMicroelectronics, Thales and TurboConcept, are already present on several markets that involve architecture of error control codes. The three companies are willing to exploit new disruptive technology for commercial exploitation of error control codes in both point to point and broadcast wireless communications.
Several scientists have recently tackled the performance evaluation of iterative decoders in stochastic architectures (in the next generation of integrated circuits with transistor size below 40 nm, every single gate can temporarily output a wrong value due to transient defects [ITRS2013]). One of the first proposed trend has been to evaluate, both theoretically and practically, the performance degradation induced by a stochastic architecture [Ngassa2013, Ngassa2014, Dupraz2014, Tabatabaei2013, Yazdi2012], then using wisely the redundancy to reduce the negative effects introduced by the transistor noise [Tang2013]. Through these research endeavors, an unexpected spin-off was identified: the noise inside the decoders is not necessarily an enemy to combat, but it can be used as an ally. Indeed, recent works have shown that the controlled injection of noise in an iterative error control decoder can significantly enhance the error correction performance, and thus, contribute to mitigate the effect of the transmission channel perturbations [Ngassa2014, Rasheed2014, Sundararajan2014]. In other words, and even if it may appear as a paradox at first glance, noise in an iterative decoder can help to combat the channel noise!
In this context, the NAND project will allow both academic and industrial partners to share a common objective: design high-performance and low-complexity error control codes that rely on this disruptive decoding technique in order to develop differentiated products and thus increase the French industry competitiveness. The consortium will analyze, both form theoretical and practical points of view, the performance gain that can be obtained when introducing some noise in iterative LDPC and Turbo decoders. The consortium targets significant performance gain, both in the convergence domain (one order of magnitude in Signal to Noise ratio) and in the error floor region (several orders of magnitude for a given Signal to Noise ratio).
To carry out this project, all the aspects of the problem will be considered. From a theoretical point of view, the asymptotic performance of noisy decoders will be analyzed, in order to improve the performance in the convergence domain. The error floor performance analysis will consist of identifying the topological structures that prevent the decoder from converging. We will study how noise can help iterative decoders to escape from the harmful topological structures. Fast simulation tools will be developed on parallel programmable architecture to confirm experimentally the theoretical analysis. New iterative decoder architectures will be proposed to take into account digital noise generation and injection in the decoding process. A more prospective analysis will be carried out for analog noise generation. As a proof of concept, two demonstrators (LDPC, Turbo-Codes) will be implemented on FPGA cards. To finish, the NAND decoders will be incorporated into simulation chains, in order to measure their performance for non-Gaussian channels that are considered in several applications targeted by the three industrial partners (aeronautic mono-carrier channels, modulation with high number of states, fading channels, satellite channels with non-linear distortion).