Cyrille Chavet received M.S. and M.S.Ph. degrees in Computer Sciences from the Universitée Joseph Fourier, France, and the Ph.D. degree in Computer and Information Sciences from the Universitée de Bretagne Sud, France.
After 3 years of industrial experience in Europe (STMicroelectronics) in Computer-Aided Design, High Level Synthesis, digital circuits and telecommunication systems, he has spent 4 years in academia with the TIMA laboratory (Universitée Joseph fourier, Grenoble, France) and with the Lab-STICC Universitée de Bretagne-Sud at Lorient, France. He is currently an Associate Professor with the Lab-STICC Laboratory, Universitée de Bretagne-Sud.
His current research interests include high-level synthesis, communication adaptation, memory mapping problems and advanced neural network architectures. He has published more than 40 papers in edited books, journals or conference proceedings on these topics and holds 4 patents in hardware design domain.
He is co-editor of the book " Advanced Hardware Design for Error Correcting Codes" (Springer, 2014). He has organized workshops in international conferences HiPEAC (2012, 2013, 2014), GLS-VLSI (2015). He also serves as session chair in international IEEE conferences (SiPS), as PC member in international ACM/IEEE conferences (DASIP, ARC) or as a reviewer (DATE, ICASSP, ISCAS, ASAP, GLSVLSI, SIPS, DAC, FPL, DASIP...) and as reviewer for journals.
He is also co-author of a chapter of the books, High Level Synthesis: from Algorithm to Digital Circuit (Coussy P. & Morawiec A. (Eds.), Springer, 2008).